Manoj Kumar Majumder

According to our database, Manoj Kumar Majumder authored at least 24 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Flux Controlled Grounded Meminductor Emulator Using Single DVCCTA.

Nidhee Bhuwal, Kamal Solanki, Manoj Kumar Majumder, Deepika Gupta

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023

Performance Analysis of Cylindrical Through Silicon Via with Interfacial Crack.

Vandana Kumari, Maya Chandrakar, Manoj Kumar Majumder

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

2022

Signal Integrity and Power Loss Analysis for Different Bump Structures in Cylindrical TSV.

Shivangi Chandrakar, Kunal Kranti Das, Deepika Gupta, Manoj Kumar Majumder

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

2021

Role of Through Silicon Via in 3D Integration: Impact on Delay and Power.

Shivangi Chandrakar, Deepika Gupta, Manoj Kumar Majumder

J. Circuits Syst. Comput., 2021

Tunnel FET-based ultra-lightweight reconfigurable TRNG and PUF design for resource-constrained internet of things.

Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi

Int. J. Circuit Theory Appl., 2021

2020

Tunnel FET-based ultralow-power and hardware-secure circuit design considering p-i-n forward leakage.

Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi

Int. J. Circuit Theory Appl., 2020

Performance analysis of mixed CNT bundle interconnects at 10 nm technology.

Vijay Rao Kumbhare, Punya Prasanna Paltani, Manoj Kumar Majumder

IET Circuits Devices Syst., 2020

Low area overhead DPA countermeasure exploiting tunnel transistor-based random number generator.

Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi

IET Circuits Devices Syst., 2020

Signal Transmission and Reflection Losses of Cylindrical and Tapered shaped TSV in 3D Integrated Circuits.

Chopali Chanchal Sahu, Shivangi Chandrakar, Manoj Kumar Majumder

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020

A Low Voltage Discriminant Circuit for Pattern Recognition Exploiting the Asymmetrical Characteristics of Tunnel FET.

Aditya Japa, Palagani Yellappa, Venkateswarlu Gonuguntla, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Jun Rim Choi, Ramesh Vaddi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Tunnel FET ambipolarity-based energy efficient and robust true random number generator against reverse engineering attacks.

Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi

IET Circuits Devices Syst., 2019

Novel Approach for Improved Signal Integrity and Power Dissipation Using MLGNR Interconnects.

Vijay Rao Kumbhare, Punya Prasanna Paltani, Manoj Kumar Majumder

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

An Efficient Wireless Charging Technique Using Inductive and Resonant Circuits.

Purvi Agrawal, Ruchi Dhamnani, Ananya Garg, Shrivishal Tripathi, Manoj Kumar Majumder

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

Designing SRAM Using CMOS and CNTFET at 32 nm Technology.

Arushi Shrivastava, Parul Damahe, Vijay Rao Kumbhare, Manoj Kumar Majumder

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

2018

Performance Analysis of Graphene Based Optical Interconnect at Nanoscale Technology.

Balkrishna Choubey, Vijay Rao Kumbhare, Manoj Kumar Majumder

Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

2015

Crosstalk Induced Delay Analysis of Randomly Distributed Mixed CNT Bundle Interconnect.

Manoj Kumar Majumder, Pankaj Kumar Das, Vobulapuram Ramesh Kumar, Brajesh Kumar Kaushik

J. Circuits Syst. Comput., 2015

2014

Delay and crosstalk reliability issues in mixed MWCNT bundle interconnects.

Manoj Kumar Majumder, Pankaj Kumar Das, Brajesh Kumar Kaushik

Microelectron. Reliab., 2014

2013

Analysis of Crosstalk Deviation for Bundled MWCNT with Process Induced Height and Width Variations.

Jainender Kumar, Manoj Kumar Majumder, Brajesh Kumar Kaushik, Sudeb Dasgupta

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

2012

Independent Gate SRAM Based on Asymmetric Gate to Source/Drain Overlap-Underlap Device FinFET.

Naveen Kaushik, Brajesh Kumar Kaushik, Davinder Kaur, Manoj Kumar Majumder

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Low Complexity Encoder for Crosstalk Reduction in RLC Modeled Interconnects.

Gunti Nagendra Babu, Brajesh Kumar Kaushik, Anand Bulusu, Manoj Kumar Majumder

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Propagation Delay Analysis for Bundled Multi-Walled CNT in Global VLSI Interconnects.

Pankaj Kumar Das, Manoj Kumar Majumder, Brajesh Kumar Kaushik, S. K. Manhas

Proceedings of the Second International Conference on Soft Computing for Problem Solving, 2012

Comparison of crosstalk delay between single and bundled SWNT for global VLSI interconnects.

Manoj Kumar Majumder, Nisarg D. Pandya, Brajesh Kumar Kaushik, S. K. Manhas

Proceedings of the 1st International Conference on Recent Advances in Information Technology, 2012

Novel VLSI architecture for two-dimensional radon transform computations.

Baljit Kaur, Manoj Kumar Majumder

Proceedings of the 1st International Conference on Recent Advances in Information Technology, 2012

Analysis of crosstalk delay and area for MWNT and bundled SWNT in global VLSI interconnects.

Manoj Kumar Majumder, Nisarg D. Pandya, Brajesh Kumar Kaushik, S. K. Manhas

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012