S. K. Manhas

According to our database, S. K. Manhas authored at least 18 papers between 2001 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization.

Baljit Kaur, Arvind Kumar Sharma, Naushad Alam, S. K. Manhas, Bulusu Anand

Microelectron. J., 2016

FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay.

Archana Pandey, Harsh Kumar, Praanshu Goyal, Sudeb Dasgupta, S. K. Manhas, Anand Bulusu

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Metal Carbon Nanotube Schottky Barrier Diode with Detection of Polar Non-polar Gases.

Sarvesh Agarwal, S. K. Manhas, Sudeb Dasgupta, Neeraj Jain

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation.

Om. Prakash, Satish Maheshwaram, Mohit Sharma, Anand Bulusu, A. K. Saxena, S. K. Manhas

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

Lateral silicon nanowire based standard cell design for higher performance.

Om. Prakash, Mohit Sharma, Anand Bulusu, A. K. Saxena, S. K. Manhas, Satish Maheshwaram

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015

Low power SRAM design for 14 nm GAA Si-nanowire technology.

Gaurav Kaushal, H. Jeong, Satish Maheshwaram, S. K. Manhas, Sudeb Dasgupta, Seong-Ook Jung

Microelectron. J., 2015

An 8 bit, 100 kS/s, switch-capacitor DAC SAR ADC for RFID applications.

Ashish Joshi, S. K. Manhas, Satinder K. Sharma, Sudeb Dasgupta

Microelectron. J., 2015

2014

Efficient ECSM Characterization Considering Voltage, Temperature, and Mechanical Stress Variability.

Baljit Kaur, Naushad Alam, S. K. Manhas, Bulusu Anand

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2013

An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies.

Baljit Kaur, Sandeep Miryala, S. K. Manhas, Bulusu Anand

Proceedings of the International Symposium on Quality Electronic Design, 2013

2012

Propagation Delay Analysis for Bundled Multi-Walled CNT in Global VLSI Interconnects.

Pankaj Kumar Das, Manoj Kumar Majumder, Brajesh Kumar Kaushik, S. K. Manhas

Proceedings of the Second International Conference on Soft Computing for Problem Solving, 2012

Comparison of crosstalk delay between single and bundled SWNT for global VLSI interconnects.

Manoj Kumar Majumder, Nisarg D. Pandya, Brajesh Kumar Kaushik, S. K. Manhas

Proceedings of the 1st International Conference on Recent Advances in Information Technology, 2012

Analysis of crosstalk delay and area for MWNT and bundled SWNT in global VLSI interconnects.

Manoj Kumar Majumder, Nisarg D. Pandya, Brajesh Kumar Kaushik, S. K. Manhas

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

An accurate current source model for CMOS based combinational logic cell.

Baljit Kaur, Sandeep Vundavalli, S. K. Manhas, Sudeb Dasgupta, Bulusu Anand

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011

Barrier layer thickness analysis for reliable copper plug process in CMOS technology.

S. K. Manhas, N. Singh, G. Q. Lo

Microelectron. Reliab., 2011

2010

A high performance vertical Si nanowire CMOS for ultra high density circuits.

Satish Maheshwaram, Gaurav Kaushal, S. K. Manhas

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2004

Influence of mobility model on extraction of stress dependent source-drain series resistance.

Merlyne M. De Souza, S. K. Manhas, D. Chandra Sekhar, A. S. Oates, Prasad Chaparala

Microelectron. Reliab., 2004

2003

Characterisation of series resistance degradation through charge pumping technique.

S. K. Manhas, D. Chandra Sekhar, A. S. Oates, Merlyne M. De Souza

Microelectron. Reliab., 2003

2001

A comparison of early stage hot carrier degradation behaviour in 5 and 3 V sub-micron low doped drain metal oxide semiconductor field effect transistors.

Merlyne M. De Souza, J. Wang, S. K. Manhas, E. M. Sankara Narayanan, A. S. Oates

Microelectron. Reliab., 2001