Manuel Hohenauer

According to our database1, Manuel Hohenauer authored at least 13 papers between 2003 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2009
Retargetable code generation based on an architecture description language.
PhD thesis, 2009

A SIMD optimization framework for retargetable compilers.
ACM Trans. Archit. Code Optim., 2009

2008
Retargetable Code Optimization for Predicated Execution.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
ASIP architecture exploration for efficient IPSec encryption: A case study.
ACM Trans. Embed. Comput. Syst., 2007

Increasing data-bandwidth to instruction-set extensions through register clustering.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting.
J. VLSI Signal Process., 2006

An interprocedural code optimization technique for network processors using hardware multi-threading support.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Retargetable code optimization with SIMD instructions.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005
C Compiler Retargeting Based on Instruction Semantics Models.
Proceedings of the 2005 Design, 2005

2004
A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models.
Proceedings of the 2004 Design, 2004

A novel approach for flexible and consistent ADL-driven ASIP design.
Proceedings of the 41th Design Automation Conference, 2004

2003
Instruction Scheduler Generation for Retargetable Compilation.
IEEE Des. Test Comput., 2003

Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models.
Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003


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