Kingshuk Karuri

According to our database1, Kingshuk Karuri authored at least 16 papers between 2004 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs).
Proceedings of the Embedded Computer Systems: Architectures, 2009

Software Instrumentation.
Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008

A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors.
ACM Trans. Embed. Comput. Syst., 2008

Multiprocessor performance estimation using hybrid simulation.
Proceedings of the 45th Design Automation Conference, 2008

ASIP architecture exploration for efficient IPSec encryption: A case study.
ACM Trans. Embed. Comput. Syst., 2007

Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

Increasing data-bandwidth to instruction-set extensions through register clustering.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Design space exploration of partially re-configurable embedded processors.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Memory Access Micro-Profiling for ASIP Design.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

A design flow for configurable embedded processors based on optimized instruction set extension synthesis.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A SW performance estimation framework for early system-level-design using fine-grained instrumentation.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Design and implementation of a modular and portable IEEE 754 compliant floating-point unit.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Fine-grained application source code profiling for ASIP design.
Proceedings of the 42nd Design Automation Conference, 2005

Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models.
Proceedings of the 2004 Design, 2004