Manuel Jesús Bellido Díaz

Affiliations:
  • University of Seville, Spain


According to our database1, Manuel Jesús Bellido Díaz authored at least 37 papers between 1993 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Online presence:

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Bibliography

2021
An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation.
IEEE Access, 2021

2020
Address-encoded byte order.
Microprocess. Microsystems, 2020

Using the complement of the cosine to compute trigonometric functions.
EURASIP J. Adv. Signal Process., 2020

2017
Minimalistic SDHC-SPI hardware reader module for boot loader applications.
Microelectron. J., 2017

2016
Fast Hardware Implementations of Static P Systems.
Comput. Informatics, 2016

2012
Network Time Synchronization: A Full Hardware Approach.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

2011
Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation.
IEEE Trans. Instrum. Meas., 2011

Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells.
J. Low Power Electron., 2011

2010
Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies.
J. Low Power Electron., 2010

Design and implementation of a suitable core for on-chip long-term verification.
Proceedings of the IEEE Fifth International Symposium on Industrial Embedded Systems, 2010

2009
Efficient techniques and methodologies for embedded system design usign free hardware and open standards.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008
Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

2007
Improving the Performance of Static CMOS Gates by Using Independent Bodies.
J. Low Power Electron., 2007

Design of a FFT/IFFT module as an IP core suitable for embedded systems.
Proceedings of the IEEE Second International Symposium on Industrial Embedded Systems, 2007

Static Power Consumption in CMOS Gates Using Independent Bodies.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

2006
Accurate Logic-Level Current Estimation for Digital CMOS Circuits.
J. Low Power Electron., 2006

Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements.
Proceedings of the International Symposium on Industrial Embedded Systems, 2006

2005
Logic-Level Fast Current Simulation for Digital CMOS Circuits.
Proceedings of the Integrated Circuit and System Design, 2005

Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates.
Proceedings of the Integrated Circuit and System Design, 2005

2004
Signal Sampling Based Transition Modeling for Digital Gates Characterization.
Proceedings of the Integrated Circuit and System Design, 2004

2003
Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits.
Proceedings of the Integrated Circuit and System Design, 2003

Internode: Internal Node Logic Computational Model.
Proceedings of the Proceedings 36th Annual Simulation Symposium (ANSS-36 2003), Orlando, Florida, USA, March 30, 2003

2002
Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Characterization of Normal Propagation Delay for Delay Degradation Model (DDM).
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

2001
Gate-level simulation of CMOS circuits using the IDDM model.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

AUTODDM: automatic characterization tool for the delay degradation model.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Degradation Delay Model Extension to CMOS Gates.
Proceedings of the Integrated Circuit Design, 2000

Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits.
Proceedings of the Integrated Circuit Design, 2000

Inertial and degradation delay model for CMOS logic gates.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1998
Efficient self-timed circuits based on weak NMOS-trees.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1996
Multimedia System for Instruction and Learning Electronics.
Proceedings of the Computer Aided Learning and Instruction in Science and Engineering, 1996

1995
Modular Asynchronous Arbiter Insensitive to Metastability.
IEEE Trans. Computers, 1995

New CMOS VLSI linear self-timed architectures.
Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995

1993
A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Modeling of real bistables in VHDL.
Proceedings of the European Design Automation Conference 1993, 1993


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