José Luis Huertas

According to our database1, José Luis Huertas authored at least 92 papers between 1976 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2016
Cell-culture measurements using voltage oscillations.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

2015
The Bio-Oscillator: A Circuit for Cell-Culture Assays.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

From voltage oscillations to tissue-impedance measurements.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

2012
Multi-condition alternate test of analog, mixed-signal, and RF systems.
Proceedings of the 13th Latin American Test Workshop, 2012

OBT for settling error test of sampled-data systems using signal-dependent clocking.
Proceedings of the 17th IEEE European Test Symposium, 2012

2011
Alternate Test of LNAs Through Ensemble Learning of On-Chip Digital Envelope Signatures.
J. Electron. Test., 2011

Improving the Accuracy of RF Alternate Test Using Multi-VDD Conditions: Application to Envelope-Based Test of LNAs.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Low-cost signature test of RF blocks based on envelope response analysis.
Proceedings of the 15th European Test Symposium, 2010

(Some) Open Problems to Incorporate BIST in Complex Heterogeneous Integrated Systems.
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

2009
A BIST Solution for the Functional Characterization of RF Systems Based on Envelope Response Analysis.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
A 2.4GHz LNA in a 90-nm CMOS technology designed with ACM model.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Oscillation-Based Test in Data Converters: On-Line Monitoring.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

2007
Total ionizing dose effects in switched-capacitor filters using oscillation-based test.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

2005
Low-Voltage CMOS subthreshold log-domain filtering.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Sine-Wave Signal Characterization Using Square-Wave and SigmaDelta-Modulation: Application to Mixed-Signal BIST.
J. Electron. Test., 2005

Guest Editorial.
J. Electron. Test., 2005

Robust frequency divider based on resonant tunneling devices.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Impact of random channel mismatch on the SNR and SFDR of time-interleaved ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A true-1-V 300-μW CMOS-subthreshold log-domain hearing-aid-on-chip.
IEEE J. Solid State Circuits, 2004

Test and design-for-test of mixed-signal integrated circuits.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Test and Design-for-Test of Mixed-Signal Integrated Circuits.
Proceedings of the Information Technology, Selected Tutorials, 2004

A Method for Parameter Extraction of Analog Sine-Wave Signals for Mixed-Signal Built-In-Self-Test Applications.
Proceedings of the 2004 Design, 2004

2003
Oscillation-based test in bandpass oversampled A/D converters.
Microelectron. J., 2003

Sub-1-V CMOS proportional-to-absolute temperature references.
IEEE J. Solid State Circuits, 2003

2002
COPAS: A New Algorithm for the Partial Input Encoding Problem.
VLSI Design, 2002

Testing Mixed-Signal Cores: A Practical Oscillation-Based Test in an Analog Macrocell.
IEEE Des. Test Comput., 2002

Practical Oscillation-Based Test of Integrated Filters.
IEEE Des. Test Comput., 2002

Practical Solutions for the Application of the Oscillation-Based-Test: Start-Up and On-Chip Evaluation.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Low-cost on-chip measurements for Oscillation-Based-Test in Analog Integrated Circuits.
Proceedings of the 3rd Latin American Test Workshop, 2002

Practical solutions for the application of the oscillation-based-test in analog integrated circuits.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Simplified Reed-Muller expressions for residue threshold functions.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Practical Oscillation-Based Test in Analog Integrated Filters: Experimental Results.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2001
Efficient Realization of a Threshold Voter for Self-Purging Redundancy.
J. Electron. Test., 2001

New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters.
J. Electron. Test., 2001

Self-Testable Pipelined ADC with Low Hardware Overhead.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Structural testing of pipelined analog to digital converters.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Built-In Self-Test in Mixed-Signal ICs: A DTMF Macrocell.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Alternative DFT Strategies for High-Speed Pipelined Data Converters.
Proceedings of the 1st Latin American Test Workshop, 2000

VHDL-based behavioural description of pipeline ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters.
Proceedings of the 2000 Design, 2000

Mixed-Signal SoC Testing: Is Mixed-Signal Design-for-Test on Its Way.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
Self-Timed Boundary-Scan Cells for Multi-Chip Module Test.
J. Electron. Test., 1999

Effective oscillation-based test for application to a DTMF filter bank.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length.
Proceedings of the 1999 Design, 1999

1998
A high-Q bandpass fully differential SC filter with enhanced testability.
IEEE J. Solid State Circuits, 1998

DfT and on-line test of high-performance data converters: a practical case.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

CMOS pipelined A/D converters with concurrent error detection capability.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits.
Proceedings of the 1998 Design, 1998

Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems.
Proceedings of the 1998 Design, 1998

A Dynamic Model for the State Assignment Problem.
Proceedings of the 1998 Design, 1998

1997
Implementation of CMOS fuzzy controllers as mixed-signal integrated circuits.
IEEE Trans. Fuzzy Syst., 1997

A DFT Technique for Analog-to-Digital Converters with digital correction.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Analog and Mixed-Signal Benchmark Circuits-First Release.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

A performance-driven placement algorithm with simultaneous Place&Route optimization for analog ICs.
Proceedings of the European Design and Test Conference, 1997

SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Integrated circuit implementation of fuzzy controllers.
IEEE J. Solid State Circuits, 1996

Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

1995
A vertically integrated tool for automated design of ΣΔ modulators.
IEEE J. Solid State Circuits, July, 1995

SODS: a new CMOS differential-type structure.
IEEE J. Solid State Circuits, July, 1995

Modular Asynchronous Arbiter Insensitive to Metastability.
IEEE Trans. Computers, 1995

Constrained state assignment of easily testable FSMs.
J. Electron. Test., 1995

A solution for the on-line test of analog ladder filters.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

A Tool for Fast Mismatch Analysis of Analog Circuits.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Statistical behavioral modeling and characterization of A/D converters.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

New CMOS VLSI linear self-timed architectures.
Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995

Optimum PLA folding through boolean satisfiability.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
Programmable switched-current wave analog filters.
IEEE J. Solid State Circuits, August, 1994

A new strategy for testing analog filters.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

A Real Time Clustering CMOS Neural Engine.
Proceedings of the Advances in Neural Information Processing Systems 7, 1994

A Study of the Sensitivity of Switched-Current Wave Analog Filters to Mismatching and Clock-Feedthrough Errors.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A Low-Cost Strategy for Testing Analog Filters.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

An Algorithm for the Place-and-Route Problem in the Layout of Analog Circuits.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Modeling OpAmp-Induced Harmonic Distorition for Switched-Capacitor Sigma-Delta Modulator Design.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
A CMOS analog adaptive BAM with on-chip learning and weight refreshing.
IEEE Trans. Neural Networks, 1993

Improving the testability of switched-capacitor filters.
J. Electron. Test., 1993

A Tool for Automated Design of Sigma-Delta Modulators Using Statistical Optimization.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

A Model for VLSI Implementation of CNN Image Processing Chips Using Current-mode Techniques.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Easily Testable PLA-based FSMS.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Modeling of real bistables in VHDL.
Proceedings of the European Design Automation Conference 1993, 1993

1992
Testability in analogue cellular neural networks.
Int. J. Circuit Theory Appl., 1992

On-line testing of switched-capacitor filters.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Accuate simplification of large symbolic formulae.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1991
CMOS Continuous BAM With On Chip Learning.
Proceedings of the Artificial Neural Networks, 1991

1990
Analysis and design of self-limiting single-OP-AMPRC oscillators.
Int. J. Circuit Theory Appl., 1990

A new method for the state reduction of incompletely specified finite sequential machines.
Proceedings of the European Design Automation Conference, 1990

1988
A new method for the efficient state-assignment of PLA-based sequential machines.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1987
Chaos from switched-capacitor circuits: Discrete maps.
Proc. IEEE, 1987

1978
On the synthesis of multivalued circuits using principally binary elements.
Proceedings of the eighth international symposium on Multiple-valued logic, 1978

Theory and design of multivalued memory elements.
Proceedings of the eighth international symposium on Multiple-valued logic, 1978

1976
Self-Synchronization of Asynchronous Sequential Circutis Employing a General Clock Function.
IEEE Trans. Computers, 1976

On Input and Next-State Equations of the <i>R-S</i> Type <i>M</i>-Stable.
IEEE Trans. Computers, 1976


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