Gustavo Wilke

According to our database1, Gustavo Wilke authored at least 14 papers between 2003 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2013
Revisiting automated physical synthesis of high-performance clock networks.
ACM Trans. Design Autom. Electr. Syst., 2013

2012
High-performance clock mesh optimization.
ACM Trans. Design Autom. Electr. Syst., 2012

Transistor sizing and gate sizing using geometric programming considering delay minimization.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

2011
Gate Sizing Minimizing Delay and Area.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010
3D-Via Driven Partitioning for 3D VLSI Integrated Circuits.
CLEI Electron. J., 2010

A Mesh-Buffer Displacement Optimization Strategy.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A study on layout quality of automatic generated cells.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Non-uniform clock mesh optimization with linear programming buffer insertion.
Proceedings of the 47th Design Automation Conference, 2010

2009
A cells and I/O pins partitioning refinement algorithm for 3D VLSI circuits.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
A novel scheme to reduce short-circuit power in mesh-based clock architectures.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

A New Clock Mesh Buffer Sizing Methodology for Skew and Power Reduction.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

2003
A Transistor Sizing Method Applied to an Automatic Layout Generation Tool.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Improving Critical Path Identification in Functional Timing Analysis.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits.
Proceedings of the Integrated Circuit and System Design, 2003


  Loading...