Gustavo Wilke

According to our database, Gustavo Wilke authored at least 17 papers between 2002 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2013

Revisiting automated physical synthesis of high-performance clock networks.

Matthew R. Guthaus, Gustavo Wilke, Ricardo Reis

ACM Trans. Design Autom. Electr. Syst., 2013

2012

High-performance clock mesh optimization.

Matthew R. Guthaus, Xuchu Hu, Gustavo Wilke, Guilherme Flach, Ricardo Reis

ACM Trans. Design Autom. Electr. Syst., 2012

Transistor sizing and gate sizing using geometric programming considering delay minimization.

Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis

Proceedings of the 10th IEEE International NEWCAS Conference, 2012

2011

Gate Sizing Minimizing Delay and Area.

Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010

3D-Via Driven Partitioning for 3D VLSI Integrated Circuits.

Sandro Sawicki, Gustavo Wilke, Marcelo O. Johann, Ricardo Reis

CLEI Electron. J., 2010

Variability-aware physical design techniques.

Gustavo Wilke, Ricardo Reis

Proceedings of the 11th Latin American Test Workshop, 2010

A Mesh-Buffer Displacement Optimization Strategy.

Guilherme Flach, Gustavo Wilke, Marcelo O. Johann, Ricardo Reis

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A study on layout quality of automatic generated cells.

Gracieli Posser, Adriel Ziesemer, Daniel Guimares Jr., Gustavo Wilke, Ricardo A. L. Reis

Proceedings of the 17th IEEE International Conference on Electronics, 2010

Non-uniform clock mesh optimization with linear programming buffer insertion.

Matthew R. Guthaus, Gustavo Wilke, Ricardo Reis

Proceedings of the 47th Design Automation Conference, 2010

2009

A cells and I/O pins partitioning refinement algorithm for 3D VLSI circuits.

Sandro Sawicki, Gustavo Wilke, Marcelo O. Johann, Ricardo Reis

Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008

A novel scheme to reduce short-circuit power in mesh-based clock architectures.

Gustavo Wilke, Renan Fonseca, Cecilia Mezzomo, Ricardo Reis

Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

A New Clock Mesh Buffer Sizing Methodology for Skew and Power Reduction.

Gustavo Wilke, Ricardo Reis

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

2003

A Transistor Sizing Method Applied to an Automatic Layout Generation Tool.

Cristiano Santos, Gustavo Wilke, Cristiano Lazzari, Ricardo Reis, José Luís Almada Güntzel

Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Improving Critical Path Identification in Functional Timing Analysis.

Daniel Lima Ferrão, Gustavo Wilke, Ricardo Augusto da Luz Reis, José Luís Almada Güntzel

Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits.

David Guerrero Martos, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán

Proceedings of the Integrated Circuit and System Design, 2003

2002

Finding the Critical Delay of Combinational Blocks by Floating Vector Simulation and Path Tracing.

Gustavo Wilke, José Luís Güntzel, Márcio Bystronski, Ana Cristina Medina Pinto, Ricardo Reis

Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

A Comparison Between Testability Measures Applied to Complex Gates.

José Luís Güntzel, Gustavo Wilke, Márcio Bystronski, Ana Cristina Medina Pinto, Ricardo Reis

Proceedings of the 3rd Latin American Test Workshop, 2002