Marefusa Kurumada

According to our database, Marefusa Kurumada authored at least 2 papers between 2000 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2008

A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues.

Satoshi Ishikura, Marefusa Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi, Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara, Hironori Akamatsu

IEEE J. Solid State Circuits, 2008

2000

An 8-ns random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D²/RAM).

Yasuhiro Agata, Kenji Motomochi, Yoshifumi Fukushima, Masanori Shirahama, Marefusa Kurumada, Naoki Kuroda, Hiroyuki Sadakata, Kohtaro Hayashi, Toshio Yamada, Kazunari Takahashi, Tsutomu Fujita

IEEE J. Solid State Circuits, 2000