Hirofumi Shinohara
Orcid: 0000-0001-5589-8397
According to our database1,
Hirofumi Shinohara
authored at least 57 papers
between 1993 and 2024.
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Bibliography
2024
A 0.116 pJ/bit Latch-Based True Random Number Generator Featuring Static Inverter Selection and Noise Enhancement.
IEEE Trans. Very Large Scale Integr. Syst., March, 2024
A Single-Inverter-Based True Random Number Generator with On-Chip Clock-Tuning-Based Entropy Calibration Circuit.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., January, 2024
2023
Practical Markov Chain and Von Neumann based Post-processing Circuits for True Random Number Generators.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
A 100-Bit-Output Modeling Attack-Resistant SPN Strong PUF with Uniform and High-Randomness Response.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A 0.186-pJ per Bit Latch-Based True Random Number Generator Featuring Mismatch Compensation and Random Noise Enhancement.
IEEE J. Solid State Circuits, 2022
A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement.
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022
A 2.17-pJ/b 5b-Response Attack-Resistant Strong PUF with Enhanced Statistical Performance.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
A 0.5-V Hybrid SRAM Physically Unclonable Function Using Hot Carrier Injection Burn-In for Stability Reinforcement.
IEEE J. Solid State Circuits, 2021
A 0.186-pJ per Bit Latch-Based True Random Number Generator with Mismatch Compensation and Random Noise Enhancement.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Session 36 Overview: Hardware Security Digital Architectures and Systems Subcommittee.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
36.3 A Modeling Attack Resilient Strong PUF with Feedback-SPN Structure Having <0.73% Bit Error Rate Through In-Cell Hot-Carrier Injection Burn-In.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
A 373-F<sup>2</sup> 0.21%-Native-BER EE SRAM Physically Unclonable Function With 2-D Power-Gated Bit Cells and ${V}_{\text{SS}}$ Bias-Based Dark-Bit Detection.
IEEE J. Solid State Circuits, 2020
An Inverter-Based True Random Number Generator with 4-bit Von-Neumann Post-Processing Circuit.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
A 0.5-V 2.07-fJ/b 497-F<sup>2</sup> EE/CMOS Hybrid SRAM Physically Unclonable Function with < 1E-7 Bit Error Rate Achieved through Hot Carrier Injection Burn-in.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
2018
Proceedings of the 2018 International Symposium on VLSI Design, 2018
A 373 F<sup>2</sup> 2D Power-Gated EE SRAM Physically Unclonable Function With Dark-Bit Detection Technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
Accurate Nanopower Supply-Insensitive CMOS Unit <i>V<sub>th</sub></i> Extractor and <i>αV<sub>th</sub></i> Extractor with Continuous Variety.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017
2016
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
Design of a Sensorless Controller Synthesized by Robust H∞ Control for Boost Converters.
IEICE Trans. Commun., 2016
2014
A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014
2013
Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: V<sub>DDmin</sub>-Aware Dual Supply Voltage Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2013
Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges.
IEEE J. Solid State Circuits, 2013
Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits.
IEEE J. Solid State Circuits, 2013
A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges.
Proceedings of the Symposium on VLSI Circuits, 2012
13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V<sub>DDmin</sub> limited ultra low voltage logic circuits.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations.
Proceedings of the 38th European Solid-State Circuit conference, 2012
Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V<sub>DD</sub>) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated V<sub>DD</sub> between flip-flops and combinational logics.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
A closed-form expression for estimating minimum operating voltage (V<sub>DDmin</sub>) of CMOS logic gates.
Proceedings of the 48th Design Automation Conference, 2011
2010
Phase-adjustable error detection flip-flops with 2-stage hold-driven optimization, slack-based grouping scheme and slack distribution control for dynamic voltage scaling.
ACM Trans. Design Autom. Electr. Syst., 2010
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2009
Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access.
IEEE J. Solid State Circuits, 2009
2008
A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die.
IEEE J. Solid State Circuits, 2008
A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations.
IEEE J. Solid State Circuits, 2008
A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues.
IEEE J. Solid State Circuits, 2008
IEICE Trans. Electron., 2008
A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology.
IEICE Trans. Electron., 2008
Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect.
Proceedings of the ESSCIRC 2008, 2008
Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling.
Proceedings of the 45th Design Automation Conference, 2008
2007
A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits.
IEEE J. Solid State Circuits, 2007
A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2005
Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
1996
IEEE J. Solid State Circuits, 1996
IEEE J. Solid State Circuits, 1996
1995
1993
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993