Toshio Terano

According to our database1, Toshio Terano authored at least 4 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
A 2.97μm-Pitch Event-Based Vision Sensor with Shared Pixel Front-End Circuitry and Low-Noise Intensity Readout Mode.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2008
A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations.
IEEE J. Solid State Circuits, 2008

A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues.
IEEE J. Solid State Circuits, 2008

2007
A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007


  Loading...