Martine D. F. Schlag

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

2000

Distributed-memory parallel routing for field-programmable gatearrays.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

New parallelization and convergence results for NC: a negotiation-based FPGA router.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

1999

Multilevel spectral hypergraph partitioning with arbitrary vertex sizes.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1997

Hybrid spectral/iterative partitioning.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Acceleration of an FPGA router.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 1997

1996

Spectral-based multiway FPGA partitioning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Detection of Multiple Faults in Two-Dimensional ILAs.

[BibT_eX]

[DOI]

F. Joel Ferguson

IEEE Trans. Computers, 1996

Multi-level spectral hypergraph partitioning with arbitrary vertex sizes.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995

Spectral-Based Multi-Way FPGA Partitioning.

[BibT_eX]

[DOI]

Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

1994

Routability-driven technology mapping for lookup table-based FPGA's.

[BibT_eX]

[DOI]

Jackson Kong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Spectral K-way ratio-cut partitioning and clustering.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

1993

Empirical evaluation of multilevel logic minimization tools for a lookup-table-based field-programmable gate array technology.

[BibT_eX]

[DOI]

Jackson Kong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Single-Layer Cylindrical Compaction.

[BibT_eX]

[DOI]

Richard Anderson

Simon Kahan

Algorithmica, 1993

Spectral K-Way Ratio-Cut Partitioning and Clustering.

[BibT_eX]

[DOI]

Proceedings of the 30th Design Automation Conference. Dallas, 1993

On Routability Prediction for Field-Programmable Gate Arrays.

[BibT_eX]

[DOI]

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1992

Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs.

[BibT_eX]

[DOI]

Jackson Kong

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1991

Delay optimization of carry-skip adders and block carry-lookahead adders.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Symposium on Computer Arithmetic, 1991

1990

Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1990

1989

Bounds on signal delay in RC mesh networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

An O(n log n) Algorithm for 1-D Tile Compaction.

[BibT_eX]

[DOI]

Richard Anderson

Simon Kahan

Proceedings of the Graph-Theoretic Concepts in Computer Science, 1989

An O(n log n) algorithm for 1-D tile compaction.

[BibT_eX]

[DOI]

Richard Anderson

Simon Kahan

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1987

Rectilinear Shortest Paths and Minimum Spanning Trees in the Presence of Rectilinear Obstacles.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1987

The planar topology of functional programs.

[BibT_eX]

[DOI]

Proceedings of the Functional Programming Languages and Computer Architecture, 1987

1986

On some union and intersection problems for polygons with fixed orientations.

[BibT_eX]

[DOI]

Computing, 1986

1985

A Method for Improving Cascode-Switch Macro Wirability.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985

vFP: An Environment for the Multi-level Specification, Analysis, and Synthesis of Hardware Algorithms.

[BibT_eX]

[DOI]

Dorab Patel

Milos D. Ercegovac

Proceedings of the Functional Programming Languages and Computer Architecture, 1985

1984

Maximizing pin alignment by pin permutations.

[BibT_eX]

[DOI]

Lin S. Woo

Chak-Kuen Wong

Integr., 1984

1983

An algorithm for optimal two-dimensional compaction of VLSI layouts.

[BibT_eX]

[DOI]