Vojin G. Oklobdzija

According to our database, Vojin G. Oklobdzija authored at least 81 papers between 1982 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2015

Minimizing Energy by Achieving Optimal Sparseness in Parallel Adders.

Mustafa Aktan, Dursun Baran, Vojin G. Oklobdzija

Proceedings of the 22nd IEEE Symposium on Computer Arithmetic, 2015

2011

A Quick Method for Energy Optimized Gate Sizing of Digital Circuits.

Mustafa Aktan, Dursun Baran, Vojin G. Oklobdzija

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Multiplier structures for low power applications in deep-CMOS.

Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

Energy-Efficient Design Methodologies: High-Performance VLSI Adders.

Bart R. Zeydel, Dursun Baran, Vojin G. Oklobdzija

IEEE J. Solid State Circuits, 2010

Low-Power Soft Error Hardened Latch.

Hossein Karimiyan Alidash, Vojin G. Oklobdzija

J. Low Power Electron., 2010

Design of a link-controller architecture for multiple serial link protocols.

Lei Wang, Pawankumar Hegde, Vishal Nawathe, Roman Staszewski, Poras T. Balsara, Vojin G. Oklobdzija

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Computing at the ultimate low-energy limits.

Vojin G. Oklobdzija

Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Energy efficient implementation of parallel CMOS multipliers with improved compressors.

Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

2009

A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR).

Milena Vratonjic, Matthew M. Ziegler, George Gristede, Victor V. Zyuban, Thomas Mitchell, Ee Cho, Chandu Visweswariah, Vojin G. Oklobdzija

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

2008

Reduced Instruction Set Computing.

Vojin G. Oklobdzija

Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008

Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits.

Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements.

Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

2007

The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements.

Christophe Giacomotto, Nikola Nedovic, Vojin G. Oklobdzija

IEEE J. Solid State Circuits, 2007

Logic Style Comparison for Ultra Low Power Operation in 65nm Technology.

Mandeep Singh, Christophe Giacomotto, Bart R. Zeydel, Vojin G. Oklobdzija

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

2006

Energy optimization of pipelined digital systems using circuit sizing and supply scaling.

Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija

IEEE Trans. Very Large Scale Integr. Syst., 2006

A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS.

Steven K. Hsu, Sanu K. Mathew, Mark A. Anders, Bart R. Zeydel, Vojin G. Oklobdzija, Ram K. Krishnamurthy, Shekhar Y. Borkar

IEEE J. Solid State Circuits, 2006

Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations.

Bart R. Zeydel, Vojin G. Oklobdzija

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Circuit Design Style for Energy Efficiency: LSDL and Compound Domino.

Xiao Yan Yu, Robert K. Montoye, Kevin J. Nowka, Bart R. Zeydel, Vojin G. Oklobdzija

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design.

Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdzija

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Energy-Delay Space Analysis for Clocked Storage Elements Under Process Variations.

Christophe Giacomotto, Nikola Nedovic, Vojin G. Oklobdzija

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

2005

Comparison of high-performance VLSI adders in the energy-delay space.

Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy

IEEE Trans. Very Large Scale Integr. Syst., 2005

Dual-edge triggered storage elements and clocking strategy for low-power systems.

Nikola Nedovic, Vojin G. Oklobdzija

IEEE Trans. Very Large Scale Integr. Syst., 2005

A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers.

Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija

Proceedings of the Integrated Circuit and System Design, 2005

Low- and Ultra Low-Power Arithmetic Units: Design and Comparison.

Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdzija

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Architectural Considerations for Energy Efficiency.

Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Efficient Mapping of Addition Recurrence Algorithms in CMOS.

Bart R. Zeydel, Theo T. J. H. Kluter, Vojin G. Oklobdzija

Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2004

A test circuit for measurement of clocked storage element characteristics.

Nikola Nedovic, William W. Walker, Vojin G. Oklobdzija

IEEE J. Solid State Circuits, 2004

2003

Clocking and clocked storage elements in a multi-gigahertz environment.

Vojin G. Oklobdzija

IBM J. Res. Dev., 2003

Energy Optimization of High-Performance Circuits.

Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija

Proceedings of the Integrated Circuit and System Design, 2003

An efficient transistor optimizer for custom circuits.

Xiao Yan Yu, Vojin G. Oklobdzija, William W. Walker

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Area-time optimal adder with relative placement generator.

Aamir A. Farooqui, Vojin G. Oklobdzija, Sadiq M. Sait

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Energy minimization method for optimal energy-delay extraction.

Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija

Proceedings of the ESSCIRC 2003, 2003

Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders.

Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy

Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003

Tutorial: Design of Power Efficient VLSI Arithmetic: Speed and Power Trade-Offs.

Vojin G. Oklobdzija, Ram Krishnamurthy

Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003

2002

Clocking and Clocked Storage Elements in Multi-GHz Environment.

Vojin G. Oklobdzija

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Performance Comparison of VLSI Adders Using Logical Effort.

Hoang Q. Dao, Vojin G. Oklobdzija

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Optimal Sequencing Energy Allocation for CMOS Integrated Systems.

Martin Saint-Laurent, Vojin G. Oklobdzija, Simon S. Singh, Madhavan Swaminathan

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Future directions in clocking multi-ghz systems.

Vojin G. Oklobdzija, Jens Sparsø

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Conditional pre-charge techniques for power-efficient dual-edge clocking.

Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Comparative analysis of double-edge versus single-edge triggered clocked storage elements.

Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001

Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variation.

Hoang Q. Dao, Kevin J. Nowka, Vojin G. Oklobdzija

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Conditional techniques for low power consumption flip-flops.

Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Timing Characterization of Dual-edge Triggered Flip-flops.

Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

2000

Clocked CMOS adiabatic logic with integrated single-phase power-clock supply.

Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current

IEEE Trans. Very Large Scale Integr. Syst., 2000

Improved sense-amplifier-based flip-flop: design and measurements.

Borivoje Nikolic, Vojin G. Oklobdzija, Vladimir Stojanovic, Wenyan Jia, James Kar-Shing Chiu, Michael Ming-Tak Leung

IEEE J. Solid State Circuits, 2000

Hybrid latch Flip-Flop with Improved Power Efficiency.

Nikola Nedovic, Vojin G. Oklobdzija

Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

Partitioned Branch Condition Resolution Logic.

Aamir A. Farooqui, K. Wayne Current, Vojin G. Oklobdzija

Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

Dynamic Flip-Flop with Improved Power.

Nikola Nedovic, Vojin G. Oklobdzija

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1999

Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems.

Vladimir Stojanovic, Vojin G. Oklobdzija

IEEE J. Solid State Circuits, 1999

VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing.

Aamir A. Farooqui, Vojin G. Oklobdzija

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998

Optimal Circuits for Parallel Multipliers.

Paul F. Stelling, Charles U. Martel, Vojin G. Oklobdzija, R. Ravi

IEEE Trans. Computers, 1998

A unified approach in the analysis of latches and flip-flops for low-power systems.

Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Comparative analysis of latches and flip-flops for high-performance systems.

Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1997

Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply].

Vojin G. Oklobdzija, Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi

IEEE J. Solid State Circuits, 1997

Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results.

Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Implementing Multiply-Accumulate Operation in Multiplication Time.

Paul F. Stelling, Vojin G. Oklobdzija

Proceedings of the 13th Symposium on Computer Arithmetic (ARITH-13 '97), 1997

1996

Efficient realizations of squaring circuit and reciprocal used in adaptive sample rate notch filters.

Richard H. Strandberg, Luis G. Bustamante, Vojin G. Oklobdzija, Michael A. Soderstrand, Jean-Claude Duc

J. VLSI Signal Process., 1996

Design strategies for optimal hybrid final adders in a parallel multiplier.

Paul F. Stelling, Vojin G. Oklobdzija

J. VLSI Signal Process., 1996

Guest editors' introduction.

Vojin G. Oklobdzija, Belle Wei

J. VLSI Signal Process., 1996

A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach.

Vojin G. Oklobdzija, David Villeger, Simon S. Liu

IEEE Trans. Computers, 1996

An ECL gate with improved speed and low power in a BiCMOS process.

Vojin G. Oklobdzija

IEEE J. Solid State Circuits, 1996

Low-Energy Logic Circuit Techniques for Multiple-Valued Logic.

K. Wayne Current, Vojin G. Oklobdzija, Dragan Maksimovic

Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996

1995

Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology.

Vojin G. Oklobdzija, David Villeger

IEEE Trans. Very Large Scale Integr. Syst., 1995

Simulations of Interacting Many Body Systems Using P4.

R. T. Scalettar, K. J. Runge, J. Correa, P. Lee, Vojin G. Oklobdzija, J. L. Vujic

Int. J. High Speed Comput., 1995

Multithreaded Decoupled Architecture.

Mikhail N. Dorojevets, Vojin G. Oklobdzija

Int. J. High Speed Comput., 1995

Monte Carlo and molecular dynamics simulations using p4.

K. J. Runge, L. P. Lee, J. Correa, R. T. Scalettar, Vojin G. Oklobdzija

Proceedings of IPPS '95, 1995

Design Strategies for Optimal Multiplier Circuits.

Charles U. Martel, Vojin G. Oklobdzija, R. Ravi, Paul F. Stelling

Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995

1994

An integrated multiplier for complex numbers.

Vojin G. Oklobdzija, David Villeger, Thierry Soulas

J. VLSI Signal Process., 1994

An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis.

Vojin G. Oklobdzija

IEEE Trans. Very Large Scale Integr. Syst., 1994

Determination of Optimal Sizes for a First and Second Level SRAM-DRAM On-Chip Cache Combination.

Rupinder Hundal, Vojin G. Oklobdzija

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

High-Performance Computer Arithmetic and Implementations: Introduction.

Vojin G. Oklobdzija

Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

1992

Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming.

Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija

IEEE Trans. Computers, 1992

1991

Introduction.

Vojin G. Oklobdzija, Belle Wei

J. VLSI Signal Process., 1991

Improved CLA scheme with optimized delay.

Brian D. Lee, Vojin G. Oklobdzija

J. VLSI Signal Process., 1991

Delay optimization of carry-skip adders and block carry-lookahead adders.

Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija

Proceedings of the 10th IEEE Symposium on Computer Arithmetic, 1991

1988

Issues in CPU-coprocessor communication and synchronization.

Vojin G. Oklobdzija

Microprocess. Microprogramming, 1988

On Implementing Addition in VLSI Technology.

Vojin G. Oklobdzija, Earl R. Barnes

J. Parallel Distributed Comput., 1988

VLSI architecture of a real-time Wigner distribution processor for acoustic signals.

N. M. Marinovic, Vojin G. Oklobdzija, L. Roytman

Proceedings of the IEEE International Conference on Acoustics, 1988

1985

Some optimal schemes for ALU implementation in VLSI technology.

Vojin G. Oklobdzija, Earl R. Barnes

Proceedings of the 7th IEEE Symposium on Computer Arithmetic, 1985

1984

Test Generation for FET Switching Circuits.

J. Paul Roth, Vojin G. Oklobdzija, John F. Beetem

Proceedings of the Proceedings International Test Conference 1984, 1984

1982

A On-Line Square Root Algorithm.

Vojin G. Oklobdzija, Milos D. Ercegovac

IEEE Trans. Computers, 1982