Vojin G. Oklobdzija

According to our database1, Vojin G. Oklobdzija authored at least 70 papers between 1982 and 2015.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 1996, "For contributions to computer architecture.".

Timeline

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Bibliography

2015
Minimizing Energy by Achieving Optimal Sparseness in Parallel Adders.
Proceedings of the 22nd IEEE Symposium on Computer Arithmetic, 2015

2011
A Quick Method for Energy Optimized Gate Sizing of Digital Circuits.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Multiplier structures for low power applications in deep-CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
Energy-Efficient Design Methodologies: High-Performance VLSI Adders.
J. Solid-State Circuits, 2010

Low-Power Soft Error Hardened Latch.
J. Low Power Electronics, 2010

Design of a link-controller architecture for multiple serial link protocols.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Computing at the ultimate low-energy limits.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Energy efficient implementation of parallel CMOS multipliers with improved compressors.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

2009
A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR).
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Low-Power Soft Error Hardened Latch.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

2008
Reduced Instruction Set Computing.
Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008

Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits.
IEEE Trans. on Circuits and Systems, 2008

Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

2007
The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements.
J. Solid-State Circuits, 2007

Logic Style Comparison for Ultra Low Power Operation in 65nm Technology.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

2006
Energy optimization of pipelined digital systems using circuit sizing and supply scaling.
IEEE Trans. VLSI Syst., 2006

Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Circuit Design Style for Energy Efficiency: LSDL and Compound Domino.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Energy-Delay Space Analysis for Clocked Storage Elements Under Process Variations.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

2005
Comparison of high-performance VLSI adders in the energy-delay space.
IEEE Trans. VLSI Syst., 2005

Dual-edge triggered storage elements and clocking strategy for low-power systems.
IEEE Trans. VLSI Syst., 2005

A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers.
Proceedings of the Integrated Circuit and System Design, 2005

Low- and Ultra Low-Power Arithmetic Units: Design and Comparison.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Architectural Considerations for Energy Efficiency.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Efficient Mapping of Addition Recurrence Algorithms in CMOS.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2003
Clocking and clocked storage elements in a multi-gigahertz environment.
IBM Journal of Research and Development, 2003

Energy Optimization of High-Performance Circuits.
Proceedings of the Integrated Circuit and System Design, 2003

An efficient transistor optimizer for custom circuits.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Area-time optimal adder with relative placement generator.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders.
Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003

Tutorial: Design of Power Efficient VLSI Arithmetic: Speed and Power Trade-Offs.
Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003

2002
Clocking and Clocked Storage Elements in Multi-GHz Environment.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Performance Comparison of VLSI Adders Using Logical Effort.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Optimal Sequencing Energy Allocation for CMOS Integrated Systems.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Future directions in clocking multi-ghz systems.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Conditional pre-charge techniques for power-efficient dual-edge clocking.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Comparative analysis of double-edge versus single-edge triggered clocked storage elements.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variation.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Timing Characterization of Dual-edge Triggered Flip-flops.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

2000
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply.
IEEE Trans. VLSI Syst., 2000

Dynamic Flip-Flop with Improved Power.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1999
VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998
Optimal Circuits for Parallel Multipliers.
IEEE Trans. Computers, 1998

A unified approach in the analysis of latches and flip-flops for low-power systems.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Comparative analysis of latches and flip-flops for high-performance systems.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1997
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Implementing Multiply-Accumulate Operation in Multiplication Time.
Proceedings of the 13th Symposium on Computer Arithmetic (ARITH-13 '97), 1997

1996
Efficient realizations of squaring circuit and reciprocal used in adaptive sample rate notch filters.
VLSI Signal Processing, 1996

Design strategies for optimal hybrid final adders in a parallel multiplier.
VLSI Signal Processing, 1996

Guest editors' introduction.
VLSI Signal Processing, 1996

A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach.
IEEE Trans. Computers, 1996

Low-Energy Logic Circuit Techniques for Multiple-Valued Logic.
Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996

1995
Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology.
IEEE Trans. VLSI Syst., 1995

Simulations of Interacting Many Body Systems Using P4.
International Journal of High Speed Computing, 1995

Multithreaded Decoupled Architecture.
International Journal of High Speed Computing, 1995

Monte Carlo and molecular dynamics simulations using p4.
Proceedings of IPPS '95, 1995

Design Strategies for Optimal Multiplier Circuits.
Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995

1994
An integrated multiplier for complex numbers.
VLSI Signal Processing, 1994

An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis.
IEEE Trans. VLSI Syst., 1994

Determination of Optimal Sizes for a First and Second Level SRAM-DRAM On-Chip Cache Combination.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

High-Performance Computer Arithmetic and Implementations: Introduction.
Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

1992
Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming.
IEEE Trans. Computers, 1992

1991
Introduction.
VLSI Signal Processing, 1991

Improved CLA scheme with optimized delay.
VLSI Signal Processing, 1991

Delay optimization of carry-skip adders and block carry-lookahead adders.
Proceedings of the 10th IEEE Symposium on Computer Arithmetic, 1991

1988
On Implementing Addition in VLSI Technology.
J. Parallel Distrib. Comput., 1988

1985
Some optimal schemes for ALU implementation in VLSI technology.
Proceedings of the 7th IEEE Symposium on Computer Arithmetic, 1985

1984
Test Generation for FET Switching Circuits.
Proceedings of the Proceedings International Test Conference 1984, 1984

1982
A On-Line Square Root Algorithm.
IEEE Trans. Computers, 1982


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