Carl Ebeling

According to our database1, Carl Ebeling
  • authored at least 54 papers between 1984 and 2016.
  • has a "Dijkstra number"2 of three.

Awards

ACM Fellow

ACM Fellow 2011, "For contributions to the architecture and design of reconfigurable systems.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepages:

On csauthors.net:

Bibliography

2016
Stratix™ 10 High Performance Routable Clock Networks.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2012
Adding dataflow-driven execution control to a Coarse-Grained Reconfigurable Array.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Hardware Acceleration of Short Read Mapping.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2011
Crunching Large Graphs with Commodity Processors.
Proceedings of the 3rd USENIX Workshop on Hot Topics in Parallelism, 2011

Energy-efficient specialization of functional units in a coarse-grained reconfigurable array.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010
Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009
Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

SPR: an architecture-adaptive CGRA mapping tool.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2007
Abstract Verilog: A Hardware Description Language for Novice Students.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

2006
PipeRoute: a pipelining-aware router for reconfigurable architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

A type architecture for hybrid micro-parallel computers.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

A Type Architecture for Hybrid Micro-Parallel Computers.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

Configurable Computing Platforms - Promises, Promises.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005
Architecture-Adaptive Routability-Driven Placement for FPGAs.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Architecture Adaptive Routability-Driven Placement for FPGAs (abstract only).
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

2004
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture.
IEEE Trans. Computers, 2004

QuickRoute: a fast routing algorithm for pipelined architectures.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Exploration of pipelined FPGA interconnect structures.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

A compiled accelerator for biological cell signaling simulations.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

2003
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

PipeRoute: a pipelining-aware router for FPGAs.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

2001
An Emulator for Exploring RaPiD Configurable Computing Architectures.
Proceedings of the Field-Programmable Logic and Applications, 2001

2000
Distributed-memory parallel routing for field-programmable gatearrays.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

1999
Architecture Design of Reconfigurable Pipelined Datapaths.
Proceedings of the 18th Conference on Advanced Research in VLSI (ARVLSI '99), 1999

1998
Mesh routing topologies for multi-FPGA systems.
IEEE Trans. VLSI Syst., 1998

Using precomputation in architecture and logic resynthesis.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Specifying and Compiling Applications for RaPiD.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

1997
Seeking Solutions in Configurable Computing.
IEEE Computer, 1997

ChaosLAN: Design and Implementation of a Gigabit LAN Using Chaotic Routing.
Proceedings of the Parallel Computer Routing and Communication, 1997

Whither Configurable Computing?
Proceedings of the 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 1997

Mapping applications to the RaPiD configurable architecture.
Proceedings of the 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 1997

Configurable computing: the catalyst for high-performance architectures.
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1996
RaPiD - Reconfigurable Pipelined Datapath.
Proceedings of the Field-Programmable Logic, 1996

Architectural Retiming: Pipelining Latency-Constrained Circuts.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Placement and routing tools for the Triptych FPGA.
IEEE Trans. VLSI Syst., 1995

The Triptych FPGA architecture.
IEEE Trans. VLSI Syst., 1995

PathFinder: A Negotiation-based Performance-driven Router for FPGAs.
Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

On the performance of level-clocked circuits.
Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995

1994
Optimal retiming of level-clocked circuits using symmetric clock schedules.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

An FPGA for Implementing Asynchronous Circuits.
IEEE Design & Test of Computers, 1994

CRANIUM: An Interface for Message Passing on Adaptive Packet Routing Networks.
Proceedings of the Parallel Computer Routing and Communication, 1994

Mesh Routing Topologies for Multi-FPGA Systems.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1993
The chaos router chip: design and implementation of an adaptive router.
Proceedings of the VLSI 93, 1993

The practical application of retiming to the design of high-performance systems.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
MONTAGNE: An FPL for Synchronous and Asynchronous Circuits.
Proceedings of the Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31, 1992

1990
Measuring the Performance Potential of Chess Programs.
Artif. Intell., 1990

1989
Apex: two architectures for generating parametric curves and surfaces.
The Visual Computer, 1989

Pattern Knowledge and Search: The SUPREM Architecture.
Artif. Intell., 1989

WireLisp: combining graphics and procedures in a circuit specification language.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988
GeminiII: a second generation layout validation program.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1986
The SUPREM Architecture: A New Intelligent Paradigm.
Artif. Intell., 1986

1984
The Design and Implementation of a VLSI Chess Move Generator.
Proceedings of the 11th Annual Symposium on Computer Architecture, 1984


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