Masamoto Tago

According to our database1, Masamoto Tago authored at least 7 papers between 2003 and 2010.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2010
An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing.
IEEE J. Solid State Circuits, 2010

2009
A 3-D Packaging Technology with Highly-Parallel Memory/Logic Interconnect.
IEICE Trans. Electron., 2009

Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2007
A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link.
IEEE J. Solid State Circuits, 2007

Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link.
IEICE Trans. Electron., 2007

2006
A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2003
Ultra-high-density interconnection technology of three-dimensional packaging.
Microelectron. Reliab., 2003


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