Kei Shiraishi

According to our database1, Kei Shiraishi authored at least 9 papers between 2011 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021

2016
6.7 A 1.2e- temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A single-slope based low-noise ADC with input-signal-dependent multiple sampling scheme for CMOS image sensors.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A power supply noise cancellation scheme for a 2.24-GHz 6-bit current-steering DAC.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Network-Resource Isolation for Virtualization Nodes.
IEICE Trans. Commun., 2013

Federation-less-federation of network-virtualization platforms.
Proceedings of the 2013 IFIP/IEEE International Symposium on Integrated Network Management (IM 2013), 2013

2012
Network-virtualization nodes that support mutually independent development and evolution of node components.
Proceedings of the IEEE International Conference on Communication Systems, 2012

2011
Current-Steering Digital-to-Analog Converter With a High-PSRR Current Switch.
IEEE Trans. Circuits Syst. II Express Briefs, 2011


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