Farhad Mehdipour
According to our database1,
Farhad Mehdipour
authored at least 61 papers
between 1999 and 2020.
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Bibliography
2020
Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering, 2020
2019
Smart Learn. Environ., 2019
Proceedings of the pHealth 2019 - Proceedings of the 16th International Conference on Wearable Micro and Nano Technologies for Personalized Health, 2019
Supercomputer Networks in the Datacenter: Benchmarking the Evolution of Communication Granularity from Macroscale down to Nanoscale.
Proceedings of the 29th International Telecommunication Networks and Applications Conference, 2019
Proceedings of the 2019 IEEE Intl Conf on Dependable, 2019
Commercial Security Scanning: Point-on-Sale (POS) Vulnerability and Mitigation Techniques.
Proceedings of the 2019 IEEE Intl Conf on Dependable, 2019
Proceedings of the Fog and Edge Computing, 2019
2018
Proceedings of the International Conference on Learning and Teaching in Computing and Engineering, 2018
2017
Performance evaluation metrics for ring-oscillator-based temperature sensors on FPGAs: A quality factor.
Integr., 2017
2016
A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias.
Microprocess. Microsystems, 2016
J. Parallel Distributed Comput., 2016
Adaptive low-complexity motion estimation algorithm for high efficiency video coding encoder.
IET Image Process., 2016
Proceedings of the 14th Annual Conference on Privacy, Security and Trust, 2016
Proceedings of the Fifth International Conference on Network, Communication and Computing, 2016
Proceedings of the 2016 IEEE 14th Intl Conf on Dependable, 2016
2015
ACM J. Emerg. Technol. Comput. Syst., 2015
Int. J. Big Data Intell., 2015
Dynamic Task Priority Scaling for Thermal Management of Multi-core Processors with Heavy Workload.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Exploring Efficiency of Ring Oscillator-Based Temperature Sensor Networks on FPGAs (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015
2014
IEICE Trans. Electron., 2014
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
A Design Methodology for Performance Maintenance of 3D Network-on-Chip with Multiplexed Through-Silicon Vias.
Proceedings of the 3rd International Workshop on Many-core Embedded Systems (MES'2015) held on June 13, 2014
Smart Field Monitoring: An Application of Cyber-Physical Systems in Agriculture (Work in Progress).
Proceedings of the IIAI 3rd International Conference on Advanced Applied Informatics, 2014
Fast center search algorithm with hardware implementation for motion estimation in HEVC encoder.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
A neuro-fuzzy fan speed controller for dynamic thermal management of multi-core processors.
Proceedings of the Computing Frontiers Conference, CF'14, 2014
Physical-aware task migration algorithm for dynamic thermal management of SMT multi-core processors.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
Proceedings of the 2013 IEEE International Conference on Green Computing and Communications (GreenCom) and IEEE Internet of Things (iThings) and IEEE Cyber, 2013
Early stage power management for 3D FPGAs considering hierarchical routing resources.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Improving Performance and Fabrication Metrics of Three-Dimensional ICs by Multiplexing Through-Silicon Vias.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Proceedings of the 10th IEEE Consumer Communications and Networking Conference, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Improving performance and energy efficiency of embedded processors via post-fabrication instruction set customization.
J. Supercomput., 2012
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
2011
A design scheme for a reconfigurable accelerator implemented by single-flux quantum circuits.
J. Syst. Archit., 2011
Routing architecture and algorithms for a superconductivity circuits-based computing hardware.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011
A thermal-aware mapping algorithm for reducing peak temperature of an accelerator deployed in a 3D stack.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
2010
Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits.
Proceedings of the Design, Automation and Test in Europe, 2010
2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
J. Supercomput., 2008
A Reconfigurable Functional Unit with Conditional Execution for Multi-Exit Custom Instructions.
IEICE Trans. Electron., 2008
Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs.
IEICE Trans. Inf. Syst., 2007
An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor.
Proceedings of the IFIP VLSI-SoC 2007, 2007
Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007
Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
An integrated temporal partitioning and physical design framework for static compilation of reconfigurable computing systems.
Microprocess. Microsystems, 2006
Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit.
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2006
GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006
An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006
2005
A Reconfigurable Architecture for Implementing Multiple Cipher Algorithms.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005
Reducing Inter-Configuration Memory Usage and Performance Improvement in Reconfigurable Computing Systems.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005
1999
Proceedings of the International Joint Conference Neural Networks, 1999