Massimo Vatalaro
Orcid: 0000-0001-8689-4073
According to our database1,
Massimo Vatalaro
authored at least 12 papers
between 2019 and 2025.
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Bibliography
2025
Highly Stable Reconfigurable TERO PUF Architecture for Hardware Security Applications.
IEEE Trans. Very Large Scale Integr. Syst., October, 2025
Highly Stable PUFs Based on Stacked Voltage Divider for Near-Zero BER Native Sensitivity to Voltage Variations.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2025
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2025
IEEE Trans. Dependable Secur. Comput., 2025
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
Design for Reliability of Multi-Bit Operations in RRAM-Based SIMPLY Logic-in-Memory Circuits.
Proceedings of the International Conference on IC Design and Technology, 2025
Design of a Temperature-Aware Voltage Generator for 2-Bit Read Operation in STT-MRAM Based SIMPLY Architecture.
Proceedings of the International Conference on IC Design and Technology, 2025
2024
Exploring the Usage of Fast Carry Chains to Implement Multistage Ring Oscillators on FPGAs: Design and Characterization.
IEEE Trans. Very Large Scale Integr. Syst., August, 2024
2023
Experimental analysis of variability in WS<sub>2</sub>-based devices for hardware security.
CoRR, 2023
2022
Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%-1.5% Bit Instability at 0.4-1.8 V Operation in 180 nm.
IEEE J. Solid State Circuits, 2022
Stability-Area Trade-off in Static CMOS PUF Based on 4T Subthreshold Voltage Divider.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
2019
Making IoT Services Accountable: A Solution Based on Blockchain and Physically Unclonable Functions.
Proceedings of the Internet and Distributed Computing Systems, 2019