Raffaele De Rose
Orcid: 0000-0003-1184-1721
According to our database1,
Raffaele De Rose
authored at least 34 papers
between 2010 and 2023.
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Bibliography
2023
Experimental analysis of variability in WS<sub>2</sub>-based devices for hardware security.
CoRR, 2023
SIMPLY+: A Reliable STT-MRAM-Based Smart Material Implication Architecture for In-Memory Computing.
IEEE Access, 2023
Voltage Reference With Corner-Aware Replica Selection/Merging for 1.4-mV Accuracy in Harvested Systems Down to 3.9 pW, 0.2 V.
IEEE Access, 2023
2022
Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%-1.5% Bit Instability at 0.4-1.8 V Operation in 180 nm.
IEEE J. Solid State Circuits, 2022
Smart Material Implication Using Spin-Transfer Torque Magnetic Tunnel Junctions for Logic-in-Memory Computing.
CoRR, 2022
Adjusting Thermal Stability in Double-Barrier MTJ for Energy Improvement in Cryogenic STT-MRAMs.
CoRR, 2022
Stability-Area Trade-off in Static CMOS PUF Based on 4T Subthreshold Voltage Divider.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW.
IEEE J. Solid State Circuits, 2021
A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy.
Proceedings of the 47th ESSCIRC 2021, 2021
2020
Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework.
Integr., 2020
A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2, 200-μm<sup>2</sup> Area in 180nm.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
Proceedings of the 16th International Conference on Synthesis, 2019
An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Evaluating the Energy Efficiency of STT-MRAMs Based on Perpendicular MTJs with Double Reference Layers.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A portable class of 3-transistor current references with low-power sub-0.5 V operation.
Int. J. Circuit Theory Appl., 2018
Impact of the Emitter Contact Pattern in c-Si BC- BJ Solar Cells by Numerical Simulations.
Proceedings of the 4th IEEE International Forum on Research and Technology for Society and Industry, 2018
Proceedings of the 2018 International Conference on IC Design & Technology, 2018
2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Int. J. Circuit Theory Appl., 2017
Int. J. Circuit Theory Appl., 2017
Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework.
Proceedings of the 14th International Conference on Synthesis, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
2014
Circuits Syst. Signal Process., 2014
Proceedings of the Collaborative Systems for Smart Networked Environments, 2014
2012
Microelectron. Reliab., 2012
Microelectron. Reliab., 2012
2010
Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010