Mathieu Luisier
Orcid: 0000-0002-2212-7972Affiliations:
- ETH Zurich, Switzerland
According to our database1,
Mathieu Luisier
authored at least 28 papers
between 2008 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
On csauthors.net:
Bibliography
2024
Single Neuromorphic Memristor closely Emulates Multiple Synaptic Mechanisms for Energy Efficient Neural Networks.
CoRR, 2024
2023
Hermitian Pseudospectral Shattering, Cholesky, Hermitian Eigenvalues, and Density Functional Theory in Nearly Matrix Multiplication Time.
CoRR, 2023
2022
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022
InP/GaAsSb DHBTs: THz Analog Performance and Record 180-Gb/s 5.5Vppd-Swing PAM-4 DAC-Driver.
Proceedings of the 2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2022
2020
Countdown Slack: A Run-Time Library to Reduce Energy Footprint in Large-Scale MPI Applications.
IEEE Trans. Parallel Distributed Syst., 2020
A back-end, CMOS compatible ferroelectric Field Effect Transistor for synaptic weights.
CoRR, 2020
Proceedings of the European Conference on Optical Communications, 2020
2019
A Data-Centric Approach to Extreme-Scale Ab initio Dissipative Quantum Transport Simulations.
CoRR, 2019
Optimizing the data movement in quantum transport simulations via data-centric parallel programming.
Proceedings of the International Conference for High Performance Computing, 2019
A data-centric approach to extreme-scale <i>ab initio</i> dissipative quantum transport simulations.
Proceedings of the International Conference for High Performance Computing, 2019
2018
Proceedings of the 48th European Solid-State Device Research Conference, 2018
Proceedings of the 76th Device Research Conference, 2018
2016
Proceedings of the 18th International Conference on Transparent Optical Networks, 2016
Performance study of strained III-V materials for ultra-thin body transistor applications.
Proceedings of the 46th European Solid-State Device Research Conference, 2016
Effect of surface roughness and phonon scattering on extremely narrow InAs-Si Nanowire TFETs.
Proceedings of the 46th European Solid-State Device Research Conference, 2016
2015
Pushing back the limit of <i>ab-initio</i> quantum transport simulations on hybrid supercomputers.
Proceedings of the International Conference for High Performance Computing, 2015
Analysis of InAs-Si heterojunction double-gate tunnel FETs with vertical tunneling paths.
Proceedings of the 45th European Solid State Device Research Conference, 2015
2014
Analysis of InAs-Si heterojunction nanowire tunnel FETs: Extreme confinement vs. bulk.
Proceedings of the 44th European Solid State Device Research Conference, 2014
2013
Fast Methods for Computing Selected Elements of the Green's Function in Massively Parallel Nanoelectronic Device Simulations.
Proceedings of the Euro-Par 2013 Parallel Processing, 2013
Proceedings of the European Solid-State Device Research Conference, 2013
Proceedings of the European Solid-State Device Research Conference, 2013
2011
Atomistic nanoelectronic device engineering with sustained performances up to 1.44 PFlop/s.
Proceedings of the Conference on High Performance Computing Networking, 2011
2010
Parallel Comput., 2010
Atomistic Modeling of Realistically Extended Semiconductor Devices with NEMO and OMEN.
Comput. Sci. Eng., 2010
A Parallel Implementation of Electron-Phonon Scattering in Nanoelectronic Devices up to 95k Cores.
Proceedings of the Conference on High Performance Computing Networking, 2010
2008
A multi-level parallel simulation approach to electron transport in nano-scale transistors.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2008
Proceedings of the 22nd Large Installation System Administration Conference, 2008
Proceedings of the Euro-Par 2008, 2008