David Esseni

According to our database1, David Esseni authored at least 21 papers between 2001 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2013, "For contributions to characterization and modeling of mobility and quasi-ballistic transport in MOS transistors".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2021
Ferroelectric based FETs and synaptic devices for highly energy efficient computational technologies.
CoRR, 2021

Modelling and design of FTJs as high reading-impedance synaptic devices.
CoRR, 2021

2016
Supersteep retrograde doping in ferroelectric MOSFETs for sub-60mV/dec subthreshold swing.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

Performance study of strained III-V materials for ultra-thin body transistor applications.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

2015
State-of-the-art semi-classical Monte Carlo method for carrier transport in nanoscale transistors.
Proceedings of the 38th International Convention on Information and Communication Technology, 2015

Strain engineering of single-layer MoS2.
Proceedings of the 45th European Solid State Device Research Conference, 2015

Improved surface roughness modeling and mobility projections in thin film MOSFETs.
Proceedings of the 45th European Solid State Device Research Conference, 2015

2014
Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I - Device-Circuit Interaction and Evaluation at Device Level.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II-Evaluation at Circuit Level and Design Perspectives.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Performance and Impact of Process Variations in Tunnel-FET Ultra-Low Voltage Digital Circuits.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Device-circuit co-design and comparison of ultra-low voltage Tunnel-FET and CMOS digital circuits.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Analysis of TFET based 6T SRAM cells implemented with state of the art silicon nanowires.
Proceedings of the 44th European Solid State Device Research Conference, 2014

2012
Mixed FBB/RBB: A Novel Low-Leakage Technique for FinFET Forced Stacks.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A Multi-Subband Monte Carlo study of electron transport in strained SiGe n-type FinFETs.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

2011
A novel back-biasing low-leakage technique for FinFET forced stacks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
Leakage-Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2010

A numerical model for the oscillation frequency, the amplitude and the phase-noise of MOS-current-mode-logic ring oscillators.
Int. J. Circuit Theory Appl., 2010

2009
Design of Ultra-Wideband Low-Noise Amplifiers in 45-nm CMOS Technology: Comparison Between Planar Bulk and SOI FinFET Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2008
Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Design of UWB LNA in 45nm CMOS technology: Planar bulk vs. FinFET.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2001
Optimized programming of multilevel flash EEPROMs.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001


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