David Esseni
Orcid: 0000-0002-3468-5197
According to our database1,
David Esseni
authored at least 30 papers
between 2001 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2013, "For contributions to characterization and modeling of mobility and quasi-ballistic transport in MOS transistors".
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on orcid.org
On csauthors.net:
Bibliography
2023
Modelling and Simulations of Ferroelectric Materials and Ferroelectric-Based Nanoelectronic Devices.
CoRR, 2023
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
Reducing the tunneling barrier thickness of bilayer ferroelectric tunnel junctions with metallic electrodes.
Proceedings of the Device Research Conference, 2023
2022
Proceedings of the ICONS 2022: International Conference on Neuromorphic Systems, Knoxville, TN, USA, July 27, 2022
Polarization switching and AC small-signal capacitance in Ferroelectric Tunnel Junctions.
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022
Multi-level Operation of FeFETs Memristors: the Crucial Role of Three Dimensional Effects.
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022
2021
Ferroelectric based FETs and synaptic devices for highly energy efficient computational technologies.
CoRR, 2021
Operation and Design of Ferroelectric FETs for a BEOL Compatible Device Implementation.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
Polarization switching and interface charges in BEOL compatible Ferroelectric Tunnel Junctions.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
2016
Supersteep retrograde doping in ferroelectric MOSFETs for sub-60mV/dec subthreshold swing.
Proceedings of the 46th European Solid-State Device Research Conference, 2016
Performance study of strained III-V materials for ultra-thin body transistor applications.
Proceedings of the 46th European Solid-State Device Research Conference, 2016
2015
State-of-the-art semi-classical Monte Carlo method for carrier transport in nanoscale transistors.
Proceedings of the 38th International Convention on Information and Communication Technology, 2015
Proceedings of the 45th European Solid State Device Research Conference, 2015
Proceedings of the 45th European Solid State Device Research Conference, 2015
2014
Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I - Device-Circuit Interaction and Evaluation at Device Level.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II-Evaluation at Circuit Level and Design Perspectives.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Performance and Impact of Process Variations in Tunnel-FET Ultra-Low Voltage Digital Circuits.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014
Device-circuit co-design and comparison of ultra-low voltage Tunnel-FET and CMOS digital circuits.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
Analysis of TFET based 6T SRAM cells implemented with state of the art silicon nanowires.
Proceedings of the 44th European Solid State Device Research Conference, 2014
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
A Multi-Subband Monte Carlo study of electron transport in strained SiGe n-type FinFETs.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
Leakage-Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2010
A numerical model for the oscillation frequency, the amplitude and the phase-noise of MOS-current-mode-logic ring oscillators.
Int. J. Circuit Theory Appl., 2010
2009
Design of Ultra-Wideband Low-Noise Amplifiers in 45-nm CMOS Technology: Comparison Between Planar Bulk and SOI FinFET Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
2008
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001