Jude A. Rivers

According to our database, Jude A. Rivers authored at least 31 papers between 1996 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2017

Configurable Detection of SDC-causing Errors in Programs.

Qining Lu, Guanpeng Li, Karthik Pattabiraman, Meeta Sharma Gupta, Jude A. Rivers

ACM Trans. Embed. Comput. Syst., 2017

2014

SDCTune: A model for predicting the SDC proneness of an application for configurable protection.

Qining Lu, Karthik Pattabiraman, Meeta Sharma Gupta, Jude A. Rivers

Proceedings of the 2014 International Conference on Compilers, 2014

2013

Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory.

Guangyu Sun, Eren Kursun, Jude A. Rivers, Yuan Xie

ACM J. Emerg. Technol. Comput. Syst., 2013

2012

Power management of multi-core chips: Challenges and pitfalls.

Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Meeta Sharma Gupta, Michael B. Healy, Hans M. Jacobson, Indira Nair, Jude A. Rivers, Jeonghee Shin, Augusto Vega, Alan J. Weger

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Error Tolerance in Server Class Processors.

Jude A. Rivers, Meeta Sharma Gupta, Jeonghee Shin, Prabhakar Kudva, Pradip Bose

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory.

Guangyu Sun, Eren Kursun, Jude A. Rivers, Yuan Xie

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2010

SAFER: Stuck-At-Fault Error Recovery for Memories.

Nak Hee Seong, Dong Hyuk Woo, Vijayalakshmi Srinivasan, Jude A. Rivers, Hsien-Hsin S. Lee

Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Power-efficient, reliable microprocessor architectures: modeling and design methods.

Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, John A. Darringer, Meeta Sharma Gupta, Hendrik F. Hamann, Hans M. Jacobson, Prabhakar Kudva, Eren Kursun, Niti Madan, Indira Nair, Jude A. Rivers, Jeonghee Shin, Alan J. Weger, Victor V. Zyuban

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009

Reliability Challenges and System Performance at the Architecture Level.

Jude A. Rivers, Prabhakar Kudva

IEEE Des. Test Comput., 2009

Tribeca: design for PVT variations with local recovery and fine-grained adaptation.

Meeta Sharma Gupta, Jude A. Rivers, Pradip Bose, Gu-Yeon Wei, David M. Brooks

Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Scalable high performance main memory system using phase-change memory technology.

Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Jude A. Rivers

Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

2008

Phaser: Phased methodology for modeling the system-level effects of soft errors.

Jude A. Rivers, Pradip Bose, Prabhakar Kudva, John-David Wellman, Pia N. Sanda, Ethan H. Cannon, Luiz C. Alves

IBM J. Res. Dev., 2008

Metrics for Architecture-Level Lifetime Reliability Analysis.

Pradeep Ramachandran, Sarita V. Adve, Pradip Bose, Jude A. Rivers

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2008

Online Estimation of Architectural Vulnerability Factor for Soft Errors.

Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers

Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

2007

A Framework for Architecture-Level Lifetime Reliability Modeling.

Jeonghee Shin, Victor V. Zyuban, Zhigang Hu, Jude A. Rivers, Pradip Bose

Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007

Architecture-Level Soft Error Analysis: Examining the Limits of Common Assumptions.

Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers

Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007

2005

Lifetime Reliability: Toward an Architectural Solution.

Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers

IEEE Micro, 2005

Exploiting Structural Duplication for Lifetime Reliability Enhancement.

Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers

Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

SoftArch: An Architecture Level Tool for Modeling and Analyzing Soft Errors.

Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers

Proceedings of the 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June, 2005

2004

The Case for Lifetime Reliability-Aware Microprocessors.

Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers

Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

The Impact of Technology Scaling on Lifetime Reliability.

Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers

Proceedings of the 2004 International Conference on Dependable Systems and Networks (DSN 2004), 28 June, 2004

2003

Reducing instruction fetch energy with backwards branch control information and buffering.

Jude A. Rivers, Sameh W. Asaad, John-David Wellman, Jaime H. Moreno

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

1999

Active Management of Data Caches by Exploiting Reuse Information.

Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson

IEEE Trans. Computers, 1999

1998

Performance aspects of high-bandwidth multi-lateral cache organizations.

Jude A. Rivers

PhD thesis, 1998

mlcache: A Flexible Multi-Lateral Cache Simulator.

Edward S. Tam, Jude A. Rivers, Gary S. Tyson, Edward S. Davidson

Proceedings of the MASCOTS 1998, 1998

Utilizing Reuse Information in Data Cache Management.

Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, Matthew K. Farrens

Proceedings of the 12th international conference on Supercomputing, 1998

Evaluating the performance of active cache management schemes.

Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1997

On High-Bandwidth Data Cache Design for Multi-Issue Processors.

Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin

Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997

On Effective Data Supply For Multi-Issue Processors.

Jude A. Rivers, Edward S. Tam, Edward S. Davidson

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996

Performance Issues in Integrating Temporality-Based Caching with Prefetching.

Jude A. Rivers, Edward S. Davidson

Perform. Evaluation, 1996

Reducing Conflicts in Direct-Mapped Caches with a Temporality-Based Design.

Jude A. Rivers, Edward S. Davidson

Proceedings of the 1996 International Conference on Parallel Processing, 1996