Mark Oskin

Affiliations:
  • University of Washington, Seattle, Washington, USA


According to our database1, Mark Oskin authored at least 70 papers between 1998 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

Online presence:

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Bibliography

2023
Beyond Static Parallel Loops: Supporting Dynamic Task Parallelism on Manycore Architectures with Software-Managed Scratchpad Memories.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022
The BlackParrot BedRock Cache Coherence System.
CoRR, 2022

2021
Accelerating Variational Quantum Algorithms Using Circuit Concurrency.
CoRR, 2021

DUB: dynamic underclocking and bypassing in nocs for heterogeneous GPU workloads.
Proceedings of the NOCS '21: International Symposium on Networks-on-Chip, 2021

Taming the Zoo: The Unified GraphIt Compiler Framework for Novel Architectures.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020
BlackParrot: An Agile Open-Source RISC-V Multicore for Accelerator SoCs.
IEEE Micro, 2020

Experiences with ML-Driven Design: A NoC Case Study.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

2019
Vignette: Perceptual Compression for Video Storage and Processing Systems.
CoRR, 2019

Perceptual Compression for Video Storage and Processing Systems.
Proceedings of the ACM Symposium on Cloud Computing, SoCC 2019, 2019

2018
Architecture Considerations for Stochastic Computing Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Stochastic Synthesis for Stochastic Computing.
CoRR, 2018

Generic System Calls for GPUs.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Scheduling Page Table Walks for Irregular GPU Applications.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Application Codesign of Near-Data Processing for Similarity Search.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium, 2018

Architectural Support for Unlimited Memory Versioning and Renaming.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium, 2018

Snapshot-Based Synchronization: A Fast Replacement for Hand-over-Hand Locking.
Proceedings of the Euro-Par 2018: Parallel Processing, 2018

2017
GPU System Calls.
CoRR, 2017

Gravel: fine-grain GPU-initiated network messages.
Proceedings of the International Conference for High Performance Computing, 2017

Towards a Deterministic Fine-Grained Task Ordering Using Multi-Versioned Memory.
Proceedings of the 29th International Symposium on Computer Architecture and High Performance Computing, 2017

Similarity Search on Automata Processors.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

Exploring computation-communication tradeoffs in camera systems.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

A hardware-friendly bilateral solver for real-time virtual reality video.
Proceedings of High Performance Graphics, 2017

Profiling a GPU database implementation: a holistic view of GPU resource utilization on TPC-H queries.
Proceedings of the 13th International Workshop on Data Management on New Hardware, 2017

POSTER: Application-Driven Near-Data Processing for Similarity Search.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016
NCAM: Near-Data Processing for Nearest Neighbor Search.
CoRR, 2016

Near Memory Similarity Search on Automata Processors.
CoRR, 2016

Observations and opportunities in architecting shared virtual memory for heterogeneous systems.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

Disciplined Inconsistency with Consistency Types.
Proceedings of the Seventh ACM Symposium on Cloud Computing, 2016

2015
Trading Latency for Performance in Data-Intensive Applications.
login Usenix Mag., 2015

Latency-Tolerant Software Distributed Shared Memory.
Proceedings of the 2015 USENIX Annual Technical Conference, 2015

NCAM: Near-Data Processing for Nearest Neighbor Search.
Proceedings of the 2015 International Symposium on Memory Systems, 2015

SNNAP: Approximate computing on programmable SoCs via neural acceleration.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Claret: using data types for highly concurrent distributed transactions.
Proceedings of the First Workshop on Principles and Practice of Consistency for Distributed Data, 2015

A Software-Managed Approach to Die-Stacked DRAM.
Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015

2014
O-structures: semantics for versioned memory.
Proceedings of the workshop on Memory Systems Performance and Correctness, 2014

Alembic: automatic locality extraction via migration.
Proceedings of the 2014 ACM International Conference on Object Oriented Programming Systems Languages & Applications, 2014

2011
Crunching Large Graphs with Commodity Processors.
Proceedings of the 3rd USENIX Workshop on Hot Topics in Parallelism, 2011

2010
DMP: Deterministic Shared-Memory Multiprocessing.
IEEE Micro, 2010

2008
Quantum computing.
Commun. ACM, 2008

The revolution inside the box.
Commun. ACM, 2008

Microcoded Architectures for Ion-Tap Quantum Computers.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

Polymorphic On-Chip Networks.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

2007
The WaveScalar architecture.
ACM Trans. Comput. Syst., 2007

RAMP: Research Accelerator for Multiple Processors.
IEEE Micro, 2007

Architectural implications of brick and mortar silicon manufacturing.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

2006
Architectural implications of quantum computing technologies.
ACM J. Emerg. Technol. Comput. Syst., 2006

Modeling instruction placement on a spatial architecture.
Proceedings of the SPAA 2006: Proceedings of the 18th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Cambridge, Massachusetts, USA, July 30, 2006

Area-Performance Trade-offs in Tiled Dataflow Architectures.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

Research accelerator for multiple processors.
Proceedings of the 2006 IEEE Hot Chips 18 Symposium (HCS), 2006

Instruction scheduling for a tiled dataflow architecture.
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

Reducing control overhead in dataflow architectures.
Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006

2005
An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

2004
Datapath and control for quantum wires.
ACM Trans. Archit. Code Optim., 2004

Ions, atoms, and bits: An architectural approach to quantum computing.
Adv. Comput., 2004

Balancing design options with Sherpa.
Proceedings of the 2004 International Conference on Compilers, 2004

2003
Cache Coherence in Intelligent Memory Systems.
IEEE Trans. Computers, 2003

The effect of communication costs in solid-state quantum computing architectures.
Proceedings of the SPAA 2003: Proceedings of the Fifteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2003

WaveScalar.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

Building Quantum Wires: The Long and the Short of It.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

2002
Operating Systems Techniques for Parallel Computation in Intelligent Memory.
Parallel Process. Lett., 2002

Using Statistical and Symbolic Simulation for Microprocessor Performance Evaluation.
J. Instr. Level Parallelism, 2002

A Practical Architecture for Reliable Quantum Computers.
Computer, 2002

Using modern graphics architectures for general-purpose computing: a framework and analysis.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

HLSpower: Hybrid Statistical Modeling of the Superscalar Power-Performance Design Space.
Proceedings of the High Performance Computing, 2002

2000
Algorithmic Complexity with Page-Based Intelligent Memory.
Parallel Process. Lett., 2000

HLS: combining statistical and symbolic simulation to guide microprocessor designs.
Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000

Reducing Cost and Tolerating Defects in Page-based Intelligent Memory.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1999
Exploiting ILP in Page-based Intelligent Memory.
Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999

ActiveOS: Virtualizing Intelligent Memory.
Proceedings of the IEEE International Conference On Computer Design, 1999

1998
Active Pages: A Computation Model for Intelligent Memory.
Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998


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