Mei-Fang Chiang

According to our database, Mei-Fang Chiang authored at least 9 papers between 2006 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

PaCC: A Parallel Compare and Compress Codec for Area Reduction in Nonvolatile Processors.

Yiqun Wang, Yongpan Liu, Shuangchen Li, Xiao Sheng, Daming Zhang, Mei-Fang Chiang, Baiko Sai, Xiaobo Sharon Hu, Huazhong Yang

IEEE Trans. Very Large Scale Integr. Syst., 2014

2012

A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops.

Yiqun Wang, Yongpan Liu, Shuangchen Li, Daming Zhang, Bo Zhao, Mei-Fang Chiang, Yanxin Yan, Baiko Sai, Huazhong Yang

Proceedings of the 38th European Solid-State Circuit conference, 2012

A compression-based area-efficient recovery architecture for nonvolatile processors.

Yiqun Wang, Yongpan Liu, Yumeng Liu, Daming Zhang, Shuangchen Li, Baiko Sai, Mei-Fang Chiang, Huazhong Yang

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2010

Redundant via Insertion: Removing Design Rule Conflicts and Balancing via Density.

Song Chen, Jianwei Shen, Wei Guo, Mei-Fang Chiang, Takeshi Yoshimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

2009

Lagrangian Relaxation Based Inter-Layer Signal Via Assignment for 3-D ICs.

Song Chen, Liangwei Ge, Mei-Fang Chiang, Takeshi Yoshimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Lagrangian relaxation based register placement for high-performance circuits.

Mei-Fang Chiang, Takumi Okamoto, Takeshi Yoshimura

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Register placement for high-performance circuits.

Mei-Fang Chiang, Takumi Okamoto, Takeshi Yoshimura

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Full-Chip Routing Considering Double-Via Insertion.

Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2006

Novel full-chip gridless routing considering double-via insertion.

Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han

Proceedings of the 43rd Design Automation Conference, 2006