Takumi Okamoto

According to our database1, Takumi Okamoto authored at least 22 papers between 1993 and 2021.

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Bibliography

2021
A Hardware Implementation on Customizable Embedded DSP Core for Colorectal Tumor Classification with Endoscopic Video toward Real-Time Computer-Aided Diagnosais System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021

2020
Classification Method with CNN features and SVM for Computer-Aided Diagnosis System in Colorectal Magnified NBI Endoscopy.
Proceedings of the 2020 IEEE Region 10 Conference, 2020

2019
Feature Extraction of Colorectal Endoscopic Images for Computer-Aided Diagnosis with CNN.
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019

Development of In-situ Monitoring System for Crop Growth Observation.
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019

An IoT-gateway with the information-centric communication.
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019

A Hardware Implementation of Colorectal Tumor Classification for Endoscopic Video on Customizable DSP Toward Real-Time Computer-Aided Diagnosis System.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
An Image Analysis Method for Lettuce Leaf and Root Growth Analysis in Hydroponic Culture.
Proceedings of the TENCON 2018, 2018

Implementation of Computer-Aided Diagnosis System on Customizable DSP Core for Colorectal Endoscopic Images with CNN Features and SVM.
Proceedings of the TENCON 2018, 2018

2015
Image segmentation of pyramid style identifier based on Support Vector Machine for colorectal endoscopic images.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

2014
FPGA implementation of type identifier for colorectal endoscopie images with NBI magnification.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2011
Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

2010
A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors.
IEEE J. Solid State Circuits, 2010

Multiwavelet Analysis of the Solution for Physical Equations.
Int. J. Wavelets Multiresolution Inf. Process., 2010

Wire congestion aware synthesis for a dynamically reconfigurable processor.
Proceedings of the International Conference on Field-Programmable Technology, 2010

2009
Lagrangian relaxation based register placement for high-performance circuits.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations.
Proceedings of the 27th International Conference on Computer Design, 2009

Register placement for high-performance circuits.
Proceedings of the Design, Automation and Test in Europe, 2009

2006
Budgeting-free hierarchical design method for large scale and high-performance LSIs.
Proceedings of the 43rd Design Automation Conference, 2006

2004
Design methodology and tools for NEC electronics' structured ASIC ISSP.
Proceedings of the 2004 International Symposium on Physical Design, 2004

2000
C-based SoC design flow and EDA tools: an ASIC and system vendorperspective.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1996
Buffered Steiner tree construction with wire sizing for interconnect layout optimization.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1993
A new feed-through assignment algorithm based on a flow model.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993


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