Michael Canesche

Orcid: 0000-0001-7882-0787

According to our database1, Michael Canesche authored at least 20 papers between 2018 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Side-channel Elimination via Partial Control-flow Linearization.
ACM Trans. Program. Lang. Syst., June, 2023

Preparing Reproducible Scientific Artifacts using Docker.
CoRR, 2023

Gene regulatory accelerators on cloud FPGA.
Concurr. Comput. Pract. Exp., 2023

High-performance graphics processing unit-based strategy for tuning a unmanned aerial vehicle controller subject to time-delay constraints.
Concurr. Comput. Pract. Exp., 2023

Heterogeneous reconfigurable architectures for machine learning dataflows.
Concurr. Comput. Pract. Exp., 2023

Fast flow cloud: A stream dataflow framework for cloud FPGA accelerator overlays at runtime.
Concurr. Comput. Pract. Exp., 2023

A Non-Blocking Multistage Interconnection using Regular Clock Schemes for QCA Circuits.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

A Game-Based Framework to Compare Program Classifiers and Evaders.
Proceedings of the 21st ACM/IEEE International Symposium on Code Generation and Optimization, 2023

2022
Impacto de Ofuscadores e Otimizadores de Código na Acurácia de Classificadores de Programas.
Proceedings of the SBLP 2022: XXVI Brazilian Symposium on Programming Languages, Virtual Event Brazil, October 6, 2022

A polynomial time exact solution to the bit-aware register binding problem.
Proceedings of the CC '22: 31st ACM SIGPLAN International Conference on Compiler Construction, Seoul, South Korea, April 2, 2022

2021
You Only Traverse Twice: A YOTT Placement, Routing, and Timing Approach for CGRAs.
ACM Trans. Embed. Comput. Syst., 2021

TRAVERSAL: A Fast and Adaptive Graph-Based Placement and Routing for CGRAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

An Open Source Custom K-means Generator for AWS Cloud FPGA Accelerators.
Proceedings of the XI Brazilian Symposium on Computing Systems Engineering, 2021

RESHAPE: A Run-Time Dataflow Hardware-Based Mapping for CGRA Overlays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Google Colab CAD4U: Hands-On Cloud Laboratories for Digital Design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Mind the Gap: Bridging Verilog and Computer Architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A Design Exploration of Scalable Mesh-based Fully Pipelined Accelerators.
Proceedings of the International Conference on Field-Programmable Technology, 2020

2019
READY: A Fine-Grained Multithreading Overlay Framework for Modern CPU-FPGA Dataflow Applications.
ACM Trans. Embed. Comput. Syst., 2019

2018
A GPU/FPGA-Based K-Means Clustering Using a Parameterized Code Generator.
Proceedings of the Symposium on High Performance Computing Systems, 2018

Minimum Switching Networks.
Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018


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