Peter Jamieson

According to our database1, Peter Jamieson authored at least 44 papers between 2000 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A Design Exploration of Scalable Mesh-based Fully Pipelined Accelerators.
Proceedings of the International Conference on Field-Programmable Technology, 2020

GA-lapagos, an open-source c framework including a python-based system for data analysis.
Proceedings of the GECCO '20: Genetic and Evolutionary Computation Conference, 2020

2019
READY: A Fine-Grained Multithreading Overlay Framework for Modern CPU-FPGA Dataflow Applications.
ACM Trans. Embed. Comput. Syst., 2019

2018
Lessons learned on which applications benefit when implemented on CPU-FPGA heterogeneous system.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

Benchmarking Heterogeneous HPC Systems Including Reconfigurable Fabrics: Community Aspirations for Ideal Comparisons.
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018

Scalable Open-Source Reconfigurable Architecture for Bacterial Quorum Sensing Simulations.
Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018

2017
Designing a collision detection accelerator on a heterogeneous CPU-FPGA platform.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

WIP - A modification to the case study method to teach students to read academic papers.
Proceedings of the 2017 IEEE Frontiers in Education Conference, 2017

2016
A simple multi-player video game framework for experimenting and teaching cultural understanding.
Proceedings of the 20th International Academic Mindtrek Conference, 2016

A framework to help analyze if creating a game to teach a learning objective is worth the work.
Proceedings of the 2016 IEEE Frontiers in Education Conference, 2016

Improved method for creating criterion maps for automatic mind map analysis.
Proceedings of the 2016 IEEE Frontiers in Education Conference, 2016

2015
More missing the Boat - Arduino, Raspberry Pi, and small prototyping boards and engineering education needs them.
Proceedings of the 2015 IEEE Frontiers in Education Conference, 2015

Evaluating metrics for automatic mind map assessment in various classes.
Proceedings of the 2015 IEEE Frontiers in Education Conference, 2015

VerilogTown: cars, crashes and hardware design.
Proceedings of the 12th International Conference on Advances in Computer Entertainment Technology, 2015

2014
Advancing genetic algorithm approaches to field programmable gate array placement with enhanced recombination operators.
Evol. Intell., 2014

Identifying and placing heterogeneously-sized cluster groupings based on FPGA placement data.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

A methodology for identifying and placing heterogeneous cluster groups based on placement proximity data (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2013
Analyzing System-Level Information's Correlation to FPGA Placement.
ACM Trans. Reconfigurable Technol. Syst., 2013

Metaheuristic Entry Points for Harnessing Human Computation in Mainstream Games.
Proceedings of the Online Communities and Social Computing, 2013

More graph comparison techniques on mind maps to provide students with feedback.
Proceedings of the IEEE Frontiers in Education Conference, 2013

Supergenes in a genetic algorithm for heterogeneous FPGA placement.
Proceedings of the IEEE Congress on Evolutionary Computation, 2013

2012
The VTR project: architecture and CAD for FPGAs from verilog to routing.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Using modern graph analysis techniques on mind maps to help quantify learning.
Proceedings of the IEEE Frontiers in Education Conference, 2012

2011
VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling.
ACM Trans. Reconfigurable Technol. Syst., 2011

Early project based learning improvements via a "star trek engineering room" game framework, and competition.
Proceedings of the 2011 Frontiers in Education Conference, 2011

2010
Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Benchmarking and evaluating reconfigurable architectures targeting the mobile domain.
ACM Trans. Design Autom. Electr. Syst., 2010

Power Characterisation for Fine-Grain Reconfigurable Fabrics.
Int. J. Reconfigurable Comput., 2010

Revisiting Genetic Algorithms for the FPGA Placement Problem.
Proceedings of the 2010 International Conference on Genetic and Evolutionary Methods, 2010

Finding System-Level Information and Analyzing Its Correlation to FPGA Placement.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

The Mythical Creature Approach - A Simulation Alternative to Building Computer Architectures.
Proceedings of the 2010 International Conference on Frontiers in Education: Computer Science & Computer Engineering, 2010

Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

Persistent CAD for in-the-field Power Optimization.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

2009
VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Benchmarking Reconfigurable Architectures in the Mobile Domain.
Proceedings of the FCCM 2009, 2009

Harnessing Human Computation Cycles for the FPGA Placement Problem.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

2008
Towards benchmarking energy efficiency of reconfigurable architectures.
Proceedings of the FPL 2008, 2008

2007
Architecting Hard Crossbars on FPGAs and Increasing their Area Efficiency with Shadow Clusters.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

2005
A Verilog RTL Synthesis Tool for Heterogeneous FPGAs.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2003
Using System Emulation to Model Next-Generation Shared Virtual Memory Clusters.
Clust. Comput., 2003

2002
CableS: Thread Control and Memory Management Extensions for Shared Virtual Memory Clusters.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

2001
CableS : Thread Control and Memory System Extensions for Shared Virtual Memory Clusters.
Proceedings of the OpenMP Shared Memory Parallel Programming, 2001

2000
Adopting a studio-based education approach into information technology (poster session).
Proceedings of the ACM SIGCSE 4th Australasian Conference on Computer Science Education, 2000


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