Edson Borin

Orcid: 0000-0003-1783-4231

According to our database1, Edson Borin authored at least 90 papers between 2004 and 2024.

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Bibliography

2024
Homomorphic WiSARDs: Efficient Weightless Neural Network training over encrypted data.
CoRR, 2024

2023
Containers in HPC: a survey.
J. Supercomput., March, 2023

Fast selection of compiler optimizations using performance prediction with graph neural networks.
Concurr. Comput. Pract. Exp., 2023

PB<sup>3</sup>Opt: Profile-based biased Bayesian optimization to select computing clusters on the cloud.
Concurr. Comput. Pract. Exp., 2023

PANCODE: Multilevel Partitioning of Neural Networks for Constrained Internet-of-Things Devices.
IEEE Access, 2023

Computing seismic attributes with deep-learning models.
Proceedings of the International Symposium on Computer Architecture and High Performance Computing Workshops , 2023

A Self-Distributing System Framework for the Computing Continuum.
Proceedings of the 32nd International Conference on Computer Communications and Networks, 2023

2022
Program representations for predictive compilation: State of affairs in the early 20's.
J. Comput. Lang., 2022

An evaluation of fast segmented sorting implementations on GPUs.
Parallel Comput., 2022

MOSFHET: Optimized Software for FHE over the Torus.
IACR Cryptol. ePrint Arch., 2022

Homomorphic evaluation of large look-up tables for inference on human genome data in the cloud.
Proceedings of the International Symposium on Computer Architecture and High Performance Computing Workshops, 2022

2021
Revisiting the functional bootstrap in TFHE.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

Efficiency and scalability of multi-lane capsule networks (MLCN).
J. Parallel Distributed Comput., 2021

Smart selection of optimizations in dynamic compilers.
Concurr. Comput. Pract. Exp., 2021

High-performance IO for seismic processing on the cloud.
Concurr. Comput. Pract. Exp., 2021

Leveraging vCPU-utilization rates to select cost-efficient VMs for parallel workloads.
Proceedings of the UCC '21: 2021 IEEE/ACM 14th International Conference on Utility and Cloud Computing, Leicester, United Kingdom, December 6, 2021

New Optimization Sequences for Code-Size Reduction for the LLVM Compilation Infrastructure.
Proceedings of the SBLP'21: 25th Brazilian Symposium on Programming Languages, Joinville, Brazil, 27 September 2021, 2021

Selecting efficient VM types to train deep learning models on Amazon SageMaker.
Proceedings of the 33rd International Symposium on Computer Architecture and High Performance Computing, 2021

Quantifying and detecting HPC resource wastage in cloud environments.
Proceedings of the 33rd International Symposium on Computer Architecture and High Performance Computing, 2021

Employing Simulation to Facilitate the Design of Dynamic Binary Translators.
Proceedings of the 33rd IEEE International Symposium on Computer Architecture and High Performance Computing, 2021

CLAP-Bot: a framework for automatic optimization of high-performance elastic applications on the Clouds.
Proceedings of the 33rd International Symposium on Computer Architecture and High Performance Computing, 2021

2020
Fog Computing on Constrained Devices: Paving the Way for the Future IoT.
Proceedings of the Advances in Edge Computing: Massive Parallel Processing and Applications, 2020

Employing Simulation to Facilitate the Design of Dynamic Code Generators.
CoRR, 2020

Accelerating Multi-attribute Unsupervised Seismic Facies Analysis With RAPIDS.
CoRR, 2020

Fast and Low-cost Search for Efficient Cloud Configurations for HPC Workloads.
CoRR, 2020

Fog Computing on Constrained Devices: Paving the Way for the Future IoT.
CoRR, 2020

A unified model for accelerating unsupervised iterative re-ranking algorithms.
Concurr. Comput. Pract. Exp., 2020

Leveraging Constrained Devices for Custom Code Execution in the Internet of Things.
Proceedings of the Companion Proceedings of the 38th Brazilian Symposium on Computer Networks and Distributed Systems, 2020

2019
The Multi-Lane Capsule Network.
IEEE Signal Process. Lett., 2019

Fog vs. Cloud Computing: Should I Stay or Should I Go?
Future Internet, 2019

Partitioning Convolutional Neural Networks to Maximize the Inference Rate on Constrained IoT Devices.
Future Internet, 2019

The Multi-Lane Capsule Network (MLCN).
CoRR, 2019

Optimized implementation of QC-MDPC code-based cryptography.
Concurr. Comput. Pract. Exp., 2019

Exploring the Cost-benefit of AWS EC2 GPU Instances for Deep Learning Applications.
Proceedings of the 12th IEEE/ACM International Conference on Utility and Cloud Computing, 2019

Selecting Efficient Cloud Resources for HPC Workloads.
Proceedings of the 12th IEEE/ACM International Conference on Utility and Cloud Computing, 2019

Improving Virtual Machine Consolidation for Heterogeneous Cloud Computing Datacenters.
Proceedings of the 31st International Symposium on Computer Architecture and High Performance Computing, 2019

Introducing Arithmetic Failures to Accelerate QC-MDPC Code-Based Cryptography.
Proceedings of the Code-Based Cryptography - 7th International Workshop, 2019

2018
Special issue on Computer Architecture and High Performance Computing.
J. Parallel Distributed Comput., 2018

A Methodology for Optimization of Interpreters.
Proceedings of the Symposium on High Performance Computing Systems, 2018

Automatic Minimization of Execution Costs of SPITS Programs in AWS.
Proceedings of the Symposium on High Performance Computing Systems, 2018

Automatic Minimization of Execution Budgets of SPITS Programs in AWS.
Proceedings of the High Performance Computing Systems - 19th Symposium, 2018

Evaluation and Mitigation of Timing Side-Channel Leakages on Multiple-Target Dynamic Binary Translators.
Proceedings of the High Performance Computing Systems - 19th Symposium, 2018

Evaluation of Timing Side-Channel Leakage on a Multiple-Target Dynamic Binary Translator.
Proceedings of the Symposium on High Performance Computing Systems, 2018

High-Performance RISC-V Emulation.
Proceedings of the High Performance Computing Systems - 19th Symposium, 2018

Towards a High-Performance RISC-V Emulator.
Proceedings of the Symposium on High Performance Computing Systems, 2018

Partitioning Convolutional Neural Networks for Inference on Constrained Internet-of-Things Devices.
Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing, 2018

The Alberta Workloads for the SPEC CPU 2017 Benchmark Suite.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

Fog-Assisted Translation: Towards Efficient Software Emulation on Heterogeneous IoT Devices.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

Evaluating the Performance and Cost of Accelerating Seismic Processing with CUDA, OpenCL, OpenACC, and OpenMP.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium, 2018

Fog vs. cloud computing: should i stay or should i go?
Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, 2018

2017
Contextual Spaces Re-Ranking: accelerating the Re-sort Ranked Lists step on heterogeneous systems.
Concurr. Comput. Pract. Exp., 2017

Handling IoT platform heterogeneity with COISA, a compact OpenISA virtual platform.
Concurr. Comput. Pract. Exp., 2017

Beyond the Fog: Bringing Cross-Platform Code Execution to Constrained IoT Devices.
Proceedings of the 29th International Symposium on Computer Architecture and High Performance Computing, 2017

The Case for Flexible ISAs: Unleashing Hardware and Software.
Proceedings of the 29th International Symposium on Computer Architecture and High Performance Computing, 2017

Optimizing memory affinity with a hybrid compiler/OS approach.
Proceedings of the Computing Frontiers Conference, 2017

2016
A Comparative Study of SYCL, OpenCL, and OpenMP.
Proceedings of the 2016 International Symposium on Computer Architecture and High Performance Computing Workshops, 2016

PY-PITS: A Scalable Python Runtime System for the Computation of Partially Idempotent Tasks.
Proceedings of the 2016 International Symposium on Computer Architecture and High Performance Computing Workshops, 2016

An Evaluation of Segmented Sorting Strategies on GPUs.
Proceedings of the 18th IEEE International Conference on High Performance Computing and Communications; 14th IEEE International Conference on Smart City; 2nd IEEE International Conference on Data Science and Systems, 2016

2015
Accelerating engineering software on modern multi-core processors.
Adv. Eng. Softw., 2015

Performance implications of dynamic memory allocators on transactional memory systems.
Proceedings of the 20th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2015

Effective, Efficient, and Scalable Unsupervised Distance Learning in Image Retrieval Tasks.
Proceedings of the 5th ACM on International Conference on Multimedia Retrieval, 2015

SHRINK: reducing the ISA complexity via instruction recycling.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

2014
Microcode Compression Using Structured-Constrained Clustering.
Int. J. Parallel Program., 2014

A Hybrid Framework to Accelerate Adaptive Compilation Systems.
Proceedings of the Programming Languages - 18th Brazilian Symposium, 2014

Leveraging Optimization Methods for Dynamically Assisted Control-Flow Integrity Mechanisms.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

Addressing JavaScript JIT Engines Performance Quirks: A Crowdsourced Adaptive Compiler.
Proceedings of the Compiler Construction - 23rd International Conference, 2014

Compiler support for selective page migration in NUMA architectures.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013
An automatic energy consumption characterization of processors using ArchC.
J. Syst. Archit., 2013

Assessing computer performance with stocs.
Proceedings of the ACM/SPEC International Conference on Performance Engineering, 2013

Image Re-ranking Acceleration on GPUs.
Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing, 2013

Modeling virtual machines misprediction overhead.
Proceedings of the IEEE International Symposium on Workload Characterization, 2013

2012
Compressing Variable-Length Instruction Traces.
Proceedings of the 13th Symposium on Computer Systems, 2012

Exploring Dynamic Program Behavior with Frames and Phases.
Proceedings of the 13th Symposium on Computer Systems, 2012

A Database for Reproducible Computational Research.
Proceedings of the 13th Symposium on Computer Systems, 2012

ACCGen: An Automatic ArchC Compiler Generator.
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012

An ArchC approach for automatic energy consumption characterization of processors.
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012

Efficient Image Re-Ranking Computation on GPUs.
Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012

2011
Structure-Constrained Microcode Compression.
Proceedings of the 23rd International Symposium on Computer Architecture and High Performance Computing, 2011

A HW/SW co-designed heterogeneous multi-core virtual machine for energy-efficient general purpose computing.
Proceedings of the CGO 2011, 2011

LAR-CC: Large atomic regions with conditional commits.
Proceedings of the CGO 2011, 2011

2010
Trace Execution Automata in Dynamic Binary Translation.
Proceedings of the Computer Architecture, 2010

TAO: two-level atomicity for dynamic binary optimizations.
Proceedings of the CGO 2010, 2010

2009
Characterization of DBT overhead.
Proceedings of the 2009 IEEE International Symposium on Workload Characterization, 2009

Dynamic parallelization of single-threaded binary programs using speculative slicing.
Proceedings of the 23rd international conference on Supercomputing, 2009

2007
Microcode compression algorithms.
PhD thesis, 2007

2006
Clustering-Based Microcode Compression.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Software-Based Transparent and Comprehensive Control-Flow Error Detection.
Proceedings of the Fourth IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2006), 2006

2005
Efficient datapath merging for partially reconfigurable architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Dynamic binary control-flow errors detection.
SIGARCH Comput. Archit. News, 2005

2004
Fast instruction set custornization.
Proceedings of the 2nd Workshop on Embedded Systems for Real-Time Multimedia, 2004


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