Frank Sill

Orcid: 0000-0002-4028-455X

According to our database1, Frank Sill authored at least 80 papers between 2004 and 2024.

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Bibliography

2024
Modeling offshore wind farm disturbances and maintenance service responses within the scope of resilience.
Reliab. Eng. Syst. Saf., February, 2024

2023
Robust Control of Autonomous Underwater Vehicles Using Delta-Sigma-Based 1-bit Controllers.
IEEE Access, 2023

LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical Probing.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

Integrity Assessment of Maritime Object Detection Impacted by Partial Camera Obstruction.
Proceedings of the 7th International Conference on System Reliability and Safety, 2023

FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Lo-RISK: Design of a Low Optical Leakage and High Performance RISC-V Core.
Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2023

Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - A RISC-V Case Study.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Guest Editors' Introduction: SBCCI 2020.
IEEE Des. Test, 2022

Threat and Risk Scenarios for Offshore Wind Farms and an Approach to their Assessment.
Proceedings of the 19th International Conference on Information Systems for Crisis Response and Management, 2022

Partial Camera Obstruction Detection Using Single Value Image Metrics and Data Augmentation.
Proceedings of the 6th International Conference on System Reliability and Safety, 2022

Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design Techniques.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
HAMBug: A Hybrid CPU-FPGA System to Detect Race Conditions.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

TRAVERSAL: A Fast and Adaptive Graph-Based Placement and Routing for CGRAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Threat analysis of offshore wind farms by Bayesian networks - a new modeling approach.
Proceedings of the 18th International Conference on Information Systems for Crisis Response and Management, 2021


One-pass Synthesis for Field-coupled Nanocomputing Technologies.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
On the impact of the synchronization constraint and interconnections in quantum-dot cellular automata.
Microprocess. Microsystems, 2020

Near Zero-Energy Computation Using Quantum-Dot Cellular Automata.
ACM J. Emerg. Technol. Comput. Syst., 2020

Embedded real-time feature extraction for electrode inversion detection in telemedicine electrocardiograms.
Biomed. Signal Process. Control., 2020

Bail on Balancing: An Alternative Approach to the Physical Design of Field-Coupled Nanocomputing Circuits.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

A Design Exploration of Scalable Mesh-based Fully Pipelined Accelerators.
Proceedings of the International Conference on Field-Programmable Technology, 2020

ToPoliNano and fiction: Design Tools for Field-coupled Nanocomputing.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

Verification for Field-coupled Nanocomputing Circuits.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Placement and Routing for Tile-based Field-coupled Nanocomputing Circuits Is <i>NP</i>-complete (Research Note).
ACM J. Emerg. Technol. Comput. Syst., 2019

Resilient training of neural network classifiers with approximate computing techniques for hardware-optimised implementations.
IET Comput. Digit. Tech., 2019

fiction: An Open Source Framework for the Design of Field-coupled Nanocomputing Circuits.
CoRR, 2019

Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-Coupled Nanotechnologies.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

HotAging - Impact of Power Dissipation on Hardware Degradation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Impact of NBTI on Increasing the Susceptibility of FinFET to Radiation.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

SAT-Hard: A Learning-Based Hardware SAT-Solver.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Scalable design for field-coupled nanocomputing circuits.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
An Energy-Aware Model for the Logic Synthesis of Quantum-Dot Cellular Automata.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Architectures of bulk built-in current sensors for detection of transient faults in integrated circuits.
Microelectron. J., 2018

Comparative analysis of network-on-chip simulation tools.
IET Comput. Digit. Tech., 2018

Breaking Landauer's Limit\\Using Quantum-dot Cellular Automata.
CoRR, 2018

Reliable Integration of Thermal Flow Sensors into Air Data Systems.
Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018

Enhancing Fundamental Energy Limits of Field-Coupled Nanocomputing Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Exploration of the Synchronization Constraint in Quantum-dot Cellular Automata.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

An exact method for design exploration of quantum-dot cellular automata.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Single Event Upset rate determination for 65 nm SRAM bit-cell in LEO radiation environments.
Microelectron. Reliab., 2017

Towards high-sensitive built-in current sensors enabling detection of radiation-induced soft errors.
Microelectron. Reliab., 2017

Efficient and scalable cross-by-pass-mesh topology for networks-on-chip.
IET Comput. Digit. Tech., 2017

Mitigation of aging effects through selective time-borrowing and alternative path activation.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Unintrusive aging analysis based on offline learning.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016
USE: A Universal, Scalable, and Efficient Clocking Scheme for QCA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Exploration of Noise Impact on Integrated Bulk Current Sensors.
J. Electron. Test., 2016

Automatic layout integration of Bulk Built-In Current Sensors for detection of soft errors.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Pipelined SAR with comparator-based switch-capacitor residue amplification.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

A Methodology for Standard Cell Design for QCA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Low overhead in situ aging monitoring and proactive aging management.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
A novel methodology for robustness analysis of QCA circuits.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

Exploration of technology parameter values of integrated circuit technologies.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

Noise analysis of integrated bulk current sensors for detection of radiation induced soft errors.
Proceedings of the 16th Latin-American Test Symposium, 2015

2014
CLEVER: Cross-Layer Error Verification, Evaluation and Reporting.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

2013
A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Enhancement of System-Lifetime by Alternating Module Activation.
Proceedings of the Embedded Systems: Design, Analysis and Verification, 2013

A bulk built-in sensor for detection of fault attacks.
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

2012
Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode.
Microelectron. Reliab., 2012

Robust modular Bulk Built-in Current Sensors for detection of transient faults.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

2011
Evaluation of the full operational cycle of a CMOS transfer-gated photodiode active pixel.
Microelectron. J., 2011

Power-Efficient Application of Sleep Transistors to Enhance the Reliability of Integrated Circuits.
J. Low Power Electron., 2011

Reliability enhancement via Sleep Transistors.
Proceedings of the 12th Latin American Test Workshop, 2011

2009
Pipelined successive approximation conversion (PSAC) with error correction for a CMOS ophthalmic sensor.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdown.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

2008
Encountering gate oxide breakdown with shadow transistors to increase reliability.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

2007
High-speed, low-leakage integrated circuits: An evolutionary algorithm perspective.
J. Syst. Archit., 2007

Algorithm for Fast Statistical Timing Analysis.
Proceedings of the International Symposium on System-on-Chip, 2007

Design of mixed gates for leakage reduction.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Minimizing leakage: What if every gate could have its individual threshold voltage?
Proceedings of the IASTED International Conference on Artificial Intelligence and Applications, 2007

2006
Mixed Gates: Leakage Reduction techniques applied to Switches for Networks-on-Chip.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

Reduzierung des Leckstromverbrauchs mit gemischten Gattern in Deep Submicron Technologien.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

Algorithms for Leakage Reduction with Dual Threshold Design Techniques.
Proceedings of the International Symposium on System-on-Chip, 2006

Evolving High-Speed, Energy-Efficient Integrated Circuits.
Proceedings of the IEEE International Conference on Evolutionary Computation, 2006

Biologically-Inspired Optimization of Circuit Performance and Leakage: A Comparative Study.
Proceedings of the Architecture of Computing Systems, 2006

2005
Reducing Leakage with Mixed-V_th (MVT).
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Total leakage power optimization with improved mixed gates.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Verlustleistungsreduzierung bei dynamischen TSPC-Schaltungstechniken.
Proceedings of the 35. Jahrestagung der Gesellschaft für Informatik, 2005

Role-based Strategies at Example of RoboCup.
Proceedings of the IASTED International Conference on Artificial Intelligence and Applications, 2005

2004
Low power gate-level design with mixed-V<sub>th</sub> (MVT) techniques.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004


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