Michiel W. van Tol

According to our database1, Michiel W. van Tol authored at least 15 papers between 2008 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepage:

On csauthors.net:

Bibliography

2014
Emulating Asymmetric MPSoCs on the Intel SCC Many-Core Processor.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

2013
Apple-CORE: Harnessing general-purpose many-cores with hardware concurrency management.
Microprocess. Microsystems, 2013

2012
Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores.
Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2012

Apple-CORE: Microgrids of SVP Cores - Flexible, General-Purpose, Fine-Grained Hardware Concurrency Management.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
High Level Simulation of SVP Many-Core Systems.
Parallel Processing Letters, 2011

A Characterization of the SPARC T3-4 System
CoRR, 2011

Extending and Implementing the Self-adaptive Virtual Processor for Distributed Memory Architectures
CoRR, 2011

A Framework for Self-adaptive Collaborative Computing on Reconfigurable Platforms.
Proceedings of the Applications, Tools and Techniques on the Road to Exascale Computing, Proceedings of the conference ParCo 2011, 31 August, 2011

Mapping Distributed S-Net on the 48-core Intel SCC processor.
Proceedings of the 3rd Many-core Applications Research Community (MARC) Symposium. Proceedings of the 3rd MARC Symposium, 2011

Efficient Memory Copy Operations on the 48-core Intel SCC Processor.
Proceedings of the 3rd Many-core Applications Research Community (MARC) Symposium. Proceedings of the 3rd MARC Symposium, 2011

2010
Towards scalable I/O on a many-core architecture.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

An Operating System Strategy for General-purpose Parallel Computing on Many-core Architectures.
Proceedings of the High Performance Computing: From Grids and Clouds to Exascale, 2010

2009
An implementation of the SANE Virtual Processor using POSIX threads.
J. Syst. Archit., 2009

2008
An Architecture and Protocol for the Management of Resources in Ubiquitous and Heterogeneous Systems Based on the SVP Model of Concurrency.
Proceedings of the Embedded Computer Systems: Architectures, 2008

A general model of concurrency and its implementation as many-core dynamic RISC processors.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008


  Loading...