Andy D. Pimentel

According to our database1, Andy D. Pimentel authored at least 101 papers between 1995 and 2019.

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Bibliography

2019
Software Passports for Automated Performance Anomaly Detection of Cyber-Physical Systems.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

CPpf: a prefetch aware LLC partitioning approach.
Proceedings of the 48th International Conference on Parallel Processing, 2019

Optimization and deployment of CNNs at the edge: the ALOHA experience.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

2018
On the Effectiveness of Communication-Centric Modelling of Complex Embedded Systems.
Proceedings of the IEEE International Conference on Parallel & Distributed Processing with Applications, 2018

ALOHA: an architectural-aware framework for deep learning at the edge.
Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, 2018

Communication-centric analysis of complex embedded computing systems: work-in-progress.
Proceedings of the International Conference on Embedded Software, 2018

2017
DAEDALUS: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on Chips.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Scenario-Based Design Space Exploration.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Exploring Exploration: A Tutorial Introduction to Embedded Systems Design Space Exploration.
IEEE Design & Test, 2017

SysRT: A modular multiprocessor RTOS simulator for early design space exploration.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Run-time mapping algorithm for dynamic workloads using process merging transformations.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Schedulability Analysis of Non-preemptive Real-Time Scheduling for Multicore Processors with Shared Caches.
Proceedings of the 2017 IEEE Real-Time Systems Symposium, 2017

Run-time resource allocation for embedded Multiprocessor System-on-Chip using tree-based design space exploration.
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

EDiFy: An Execution time Distribution Finder.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Scenario-based run-time adaptive MPSoC systems.
Journal of Systems Architecture - Embedded Systems Design, 2016

A hierarchical run-time adaptive resource allocation framework for large-scale MPSoC systems.
Design Autom. for Emb. Sys., 2016

Improving voltage control in MV smart grids.
Proceedings of the 2016 IEEE International Conference on Smart Grid Communications, 2016

Perspectives on system-level MPSoC design space exploration.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Why Comparing System-Level MPSoC Mapping Approaches is Difficult: A Case Study.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

2015
A Hybrid Task Mapping Algorithm for Heterogeneous MPSoCs.
ACM Trans. Embedded Comput. Syst., 2015

Towards self-adaptive MPSoC systems with adaptivity throttling.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

A run-time self-adaptive resource allocation framework for MPSoC systems.
Proceedings of the European Conference on Circuit Theory and Design, 2015

Fast and precise cache performance estimation for out-of-order execution.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
A two-phase design space exploration strategy for system-level real-time application mapping onto MPSoC.
Microprocessors and Microsystems - Embedded Hardware Design, 2014

Exploring Task Mappings on Heterogeneous MPSoCs using a Bias-Elitist Genetic Algorithm.
CoRR, 2014

Using chip multithreading to speed up scenario-based design space exploration: a case study.
Proceedings of the 2014 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2014

Emulating Asymmetric MPSoCs on the Intel SCC Many-Core Processor.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

Towards Exploring Vast MPSoC Mapping Design Spaces Using a Bias-Elitist Evolutionary Approach.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

A system-level simulation framework for evaluating task migration in MPSoCs.
Proceedings of the 2014 International Conference on Compilers, 2014

2013
A system-level infrastructure for multidimensional MP-SoC design space co-exploration.
ACM Trans. Embedded Comput. Syst., 2013

Fitness Prediction Techniques for Scenario-Based Design Space Exploration.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Exploiting domain knowledge in system-level MPSoC design space exploration.
Journal of Systems Architecture - Embedded Systems Design, 2013

An iterative multi-application mapping algorithm for heterogeneous MPSoCs.
Proceedings of the 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2013

A scenario-based run-time task mapping algorithm for MPSoCs.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
A Signature-Based Power Model for MPSoC on FPGA.
VLSI Design, 2012

Introduction to special section ESTIMedia'09.
ACM Trans. Embedded Comput. Syst., 2012

Introduction to the Special Section on ESTIMedia'08.
ACM Trans. Embedded Comput. Syst., 2012

VMODEX: A novel visualization tool for rapid analysis of heuristic-based multi-objective design space exploration of heterogeneous MPSoC architectures.
Simulation Modelling Practice and Theory, 2012

Evaluation of Runtime Task Mapping Using the rSesame Framework.
Int. J. Reconfig. Comp., 2012

A High-Level Power Model for MPSoC on FPGA.
Computer Architecture Letters, 2012

Interleaving methods for hybrid system-level MPSoC design space exploration.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Design space pruning through hybrid analysis in system-level design space exploration.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A SAFE approach towards early design space exploration of fault-tolerant multimedia MPSoCs.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

Fast Scenario-Based Design Space Exploration using Feature Selection.
Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012

2011
Signature-Based Calibration of Analytical Performance Models for System-Level Design Space Exploration.
Trans. HiPEAC, 2011

Design metrics and visualization techniques for analyzing the performance of MOEAs in DSE.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not?
Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011

Techniques and Visualization Approaches for Analyzing Local and Global Pareto Optimal Sets in Multi-Objective Design Space Exploration.
Proceedings of the ARCS 2011, 2011

2010
A High-level Microprocessor Power Modeling Technique Based on Event Signatures.
Signal Processing Systems, 2010

Editorial.
Signal Processing Systems, 2010

A trace-based scenario database for high-level simulation of multimedia MP-SoCs.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Runtime Task Mapping Based on Hardware Configuration Reuse.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Scenario-based design space exploration of MPSoCs.
Proceedings of the 28th International Conference on Computer Design, 2010

VMODEX: A visualization tool for multi-objective Design Space Exploration.
Proceedings of the International Conference on Field-Programmable Technology, 2010

NASA: A generic infrastructure for system-level MP-SoC design space exploration.
Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010

Message from the chairs.
Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010

Visualization of Multi-objective Design Space Exploration for Embedded Systems.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Evaluation of runtime task mapping heuristics with rSesame - a case study.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Electronic System-Level Synthesis Methodologies.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration.
Proceedings of the Embedded Computer Systems: Architectures, 2009

System-level runtime mapping exploration of reconfigurable architectures.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Introduction.
Proceedings of the Euro-Par 2009 Parallel Processing, 2009

System-level MP-SoC design space exploration using tree visualization.
Proceedings of the 7th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2009

2009 IEEE/ACM/IFIP 7th workshop on embedded systems for Real-Time multimedia (ESTIMedia 2009).
Proceedings of the 7th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2009

2008
Calibration of Abstract Performance Models for System-Level Design Space Exploration.
Signal Processing Systems, 2008

Editorial.
Journal of Systems Architecture - Embedded Systems Design, 2008

Towards Design Space Exploration for Biological Systems.
JCP, 2008

The Artemis workbench for system-level performance evaluation of embedded systems.
IJES, 2008

System-Level Design Space Exploration of Dynamic Reconfigurable Architectures.
Proceedings of the Embedded Computer Systems: Architectures, 2008

Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study.
Proceedings of the Embedded Computer Systems: Architectures, 2008

Signature-Based Calibration of Analytical System-Level Performance Models.
Proceedings of the Embedded Computer Systems: Architectures, 2008

Daedalus: toward composable multimedia MP-SoC design.
Proceedings of the 45th Design Automation Conference, 2008

2007
Editorial.
Journal of Systems Architecture, 2007

Static priority scheduling of event-triggered real-time embedded systems.
Formal Methods in System Design, 2007

A Framework for System-Level Modeling and Simulation of Embedded Systems Architectures.
EURASIP J. Emb. Sys., 2007

Taking the example of computer systems engineering for the analysis of biological cell systems.
Biosystems, 2007

Towards Multi-application Workload Modeling in Sesame for System-Level Design Space Exploration.
Proceedings of the Embedded Computer Systems: Architectures, 2007

Signature-based Microprocessor Power Modeling for Rapid System-level Design Space Exploration.
Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007

A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

Evaluating the Design of Biological Cells Using a Computer Workbench.
Proceedings of the Proceedings 40th Annual Simulation Symposium (ANSS-40 2007), 2007

2006
Editorial.
VLSI Signal Processing, 2006

Multiobjective optimization and evolutionary algorithms for the application mapping problem in multiprocessor system-on-chip design.
IEEE Trans. Evolutionary Computation, 2006

A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels.
IEEE Trans. Computers, 2006

A Mixed-level Co-simulation Method for System-level Design Space Exploration.
Proceedings of the 2006 4th Workshop on Embedded Systems for Real-Time Multimedia, 2006

2005
A Case for Visualization-Integrated System-Level Design Space Exploration.
Proceedings of the Embedded Computer Systems: Architectures, 2005

2004
A High-Level Programming Paradigm for SystemC.
Proceedings of the Computer Systems: Architectures, 2004

IDF Models for Trace Transformations: A Case Study in Computational Refinement.
Proceedings of the Computer Systems: Architectures, 2004

Static priority scheduling of event triggered real time embedded systems.
Proceedings of the 2nd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2004), 2004

2003
A Software Framework for Efficient System-level Performance Evaluation of Embedded Systems.
Proceedings of the 2003 ACM Symposium on Applied Computing (SAC), 2003

An IDF-based trace transformation method for communication refinement.
Proceedings of the 40th Design Automation Conference, 2003

A multiobjective optimization model for exploring multiprocessor mappings of process networks.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

2002
Towards Efficient Design Space Exploration of Heterogeneous Embedded Media Systems.
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

2001
Exploring Embedded-Systems Architectures with Artemis.
IEEE Computer, 2001

Performance evaluation of the LH*lh scalable, distributed data structure for a cluster of workstations.
Proceedings of the 2001 ACM Symposium on Applied Computing (SAC), 2001

1999
TriMedia CPU64 Architecture.
Proceedings of the IEEE International Conference On Computer Design, 1999

Evaluation of LH*LH for a Multicomputer Architecture.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

1998
Design issues for high performance simulation.
Simul. Pr. Theory, 1998

1997
An Architecture Workbench for Multicomputers.
Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997

1996
Evaluation of a Mesh of Clos wormhole network.
Proceedings of the 3rd International Conference on High Performance Computing, 1996

1995
Mermaid: modelling and evaluation research in MIMD architecture design.
Proceedings of the High-Performance Computing and Networking, 1995


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