Miroslav Knezevic

According to our database1, Miroslav Knezevic authored at least 29 papers between 2008 and 2018.

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Bibliography

2018
Optimized Threshold Implementations: Securing Cryptographic Accelerators for Low-Energy and Low-Latency Applications.
IACR Cryptology ePrint Archive, 2018

2016
Low-Latency ECDSA Signature Verification - A Road Toward Safer Traffic.
IEEE Trans. VLSI Syst., 2016

2015
FIDES: Lightweight Authenticated Cipher with Side-Channel Resistance for Constrained Hardware.
IACR Cryptology ePrint Archive, 2015

Compact Implementations of Multi-Sbox Designs.
Proceedings of the Smart Card Research and Advanced Applications, 2015

2014
Low-Latency ECDSA Signature Verification - A Road Towards Safer Traffic -.
IACR Cryptology ePrint Archive, 2014

2013
SPONGENT: The Design Space of Lightweight Cryptographic Hashing.
IEEE Trans. Computers, 2013

Fides: Lightweight Authenticated Cipher with Side-Channel Resistance for Constrained Hardware.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2013, 2013

2012
Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates.
IEEE Trans. VLSI Syst., 2012

PRINCE - A Low-latency Block Cipher for Pervasive Computing Applications (Full version).
IACR Cryptology ePrint Archive, 2012

Low-Latency Encryption - Is "Lightweight = Light + Wait"?
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2012, 2012

PRINCE - A Low-Latency Block Cipher for Pervasive Computing Applications - Extended Abstract.
Proceedings of the Advances in Cryptology - ASIACRYPT 2012, 2012

2011
Efficient Hardware Implementations of Cryptographic Primitives (Efficiënte hardware implementaties van cryptografische primitieven).
PhD thesis, 2011

Tripartite modular multiplication.
Integration, 2011

SPONGENT: The Design Space of Lightweight Cryptographic Hashing.
IACR Cryptology ePrint Archive, 2011

spongent: A Lightweight Hash Function.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28, 2011

2010
Faster Interleaved Modular Multiplication Based on Barrett and Montgomery Reduction Methods.
IEEE Trans. Computers, 2010

Speeding Up Bipartite Modular Multiplication.
Proceedings of the Arithmetic of Finite Fields, Third International Workshop, 2010

Prototyping Platform for Performance Evaluation of SHA-3 Candidates.
Proceedings of the HOST 2010, 2010

Low Cost Built in Self Test for Public Key Crypto Cores.
Proceedings of the 2010 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2010

Hardware design for Hash functions.
Proceedings of the Secure Integrated Circuits and Systems, 2010

Signal Processing for Cryptography and Security Applications.
Proceedings of the Handbook of Signal Processing Systems, 2010

2009
Modular Reduction without Precomputational Phase.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

FPGA-based testing strategy for cryptographic chips: A case study on Elliptic Curve Processor for RFID tags.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

KATAN and KTANTAN - A Family of Small and Efficient Hardware-Oriented Block Ciphers.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2009

Hardware evaluation of the Luffa hash family.
Proceedings of the 4th Workshop on Embedded Systems Security, 2009

2008
Demonstration of unobservable voice over IP.
Proceedings of the 9th IEEE International Symposium on a World of Wireless, 2008

On the Practical Performance of Rateless Codes.
Proceedings of the WINSYS 2008, 2008

Modular Reduction in GF(2n) without Pre-computational Phase.
Proceedings of the Arithmetic of Finite Fields, 2nd International Workshop, 2008

On the high-throughput implementation of RIPEMD-160 hash algorithm.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008


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