Toshihiro Katashita

According to our database, Toshihiro Katashita authored at least 23 papers between 2006 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Evaluation of Side-Channel Leakage Simulation by Using EMC Macro-Model of Cryptographic Devices.

Yusuke Yano, Kengo Iokibe, Toshiaki Teshima, Yoshitaka Toyota, Toshihiro Katashita, Yohei Hori

IEICE Trans. Commun., 2021

2020

Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge-Response pair acquisition using Built-In Self-Test before shipping.

Yasuhiro Ogasahara, Yohei Hori, Toshihiro Katashita, Tomoki Iizuka, Hiromitsu Awano, Makoto Ikeda, Hanpei Koike

Integr., 2020

2019

A Deep Learning Attack Countermeasure with Intentional Noise for a PUF-Based Authentication Scheme.

Risa Yashiro, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama

Proceedings of the Innovative Security Solutions for Information Technology and Communications, 2019

2018

Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device.

Toshihiro Katashita, Masakazu Hioki, Yohei Hori, Hanpei Koike

IEICE Trans. Inf. Syst., 2018

2017

Prototype of USB stick-sized PUF module for authentication and key generation.

Toshihiro Katashita, Yohei Hori, Yasuhiro Ogasahara

Proceedings of the IEEE 6th Global Conference on Consumer Electronics, 2017

2015

A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation.

Sho Endo, Yang Li, Naofumi Homma, Kazuo Sakiyama, Kazuo Ohta, Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Jean-Luc Danger, Takafumi Aoki

IEEE Trans. Very Large Scale Integr. Syst., 2015

2014

Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays.

Yohei Hori, Hyunho Kang, Toshihiro Katashita, Akashi Satoh, Shin-ichi Kawamura, Kazukuni Kobara

J. Inf. Process., 2014

Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage.

Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Shivam Bhasin, Jean-Luc Danger

IEICE Trans. Electron., 2014

2013

Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption.

Yohei Hori, Toshihiro Katashita, Hirofumi Sakane, Kenji Toda, Akashi Satoh

IEICE Trans. Inf. Syst., 2013

A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation.

Daisuke Fujimoto, Toshihiro Katashita, Akihiko Sasaki, Yohei Hori, Akashi Satoh, Makoto Nagata

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

A novel smart card development platform for evaluating physical attacks and PUFs.

Toshihiro Katashita, Akihiko Sasaki, Yohei Hori

Proceedings of the IEEE 2nd Global Conference on Consumer Electronics, 2013

Energy and area saving effect of Dynamic Partial Reconfiguration on a 28-nm process FPGA.

Yohei Hori, Toshihiro Katashita, Kazukuni Kobara

Proceedings of the IEEE 2nd Global Conference on Consumer Electronics, 2013

2012

Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates.

Miroslav Knezevic, Kazuyuki Kobayashi, Jun Ikegami, Shin'ichiro Matsuo, Akashi Satoh, Ünal Koçabas, Junfeng Fan, Toshihiro Katashita, Takeshi Sugawara, Kazuo Sakiyama, Ingrid Verbauwhede, Kazuo Ohta, Naofumi Homma, Takafumi Aoki

IEEE Trans. Very Large Scale Integr. Syst., 2012

Circuit Simulation for Fault Sensitivity Analysis and Its Application to Cryptographic LSI.

Takeshi Sugawara, Daisuke Suzuki, Toshihiro Katashita

Proceedings of the 2012 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2012

2011

Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function.

Yohei Hori, Hyunho Kang, Toshihiro Katashita, Akashi Satoh

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

A fast power current analysis methodology using capacitor charging model for side channel attack evaluation.

Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Akihiro T. Sasaki, Yohei Hori, Akashi Satoh

Proceedings of the HOST 2011, 2011

2010

Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs.

Yohei Hori, Takahiro Yoshida, Toshihiro Katashita, Akashi Satoh

Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Hardware Implementations of Hash Function Luffa.

Akashi Satoh, Toshihiro Katashita, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki

Proceedings of the HOST 2010, 2010

2009

Development of side-channel attack standard evaluation environment.

Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008

Enhanced Correlation Power Analysis Using Key Screening Technique.

Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki

Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

2007

FPGA-Based Intrusion Detection System for 10 Gigabit Ethernet.

Toshihiro Katashita, Yoshinori Yamaguchi, Atusi Maeda, Kenji Toda

IEICE Trans. Inf. Syst., 2007

2006

A Method of Generating Highly Efficient String Matching Circuit for Intrusion Detection.

Toshihiro Katashita, Atusi Maeda, Kenji Toda, Yoshinori Yamaguchi

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Highly Efficient String Matching Circuit for IDS with FPGA.

Toshihiro Katashita, Atusi Maeda, Kenji Toda, Yoshinori Yamaguchi

Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006