Arun K. Kanuparthi

According to our database1, Arun K. Kanuparthi authored at least 15 papers between 2010 and 2022.

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Bibliography

2022
AntiDOTE: Protecting Debug Against Outsourced Test Entities.
IEEE Trans. Emerg. Top. Comput., 2022

RTL-ConTest: Concolic Testing on RTL for Detecting Security Vulnerabilities.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2019
HardFails: Insights into Software-Exploitable Hardware Bugs.
Proceedings of the 28th USENIX Security Symposium, 2019

Formal Verification of Security Critical Hardware-Firmware Interactions in Commercial SoCs.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
When a Patch is Not Enough - HardFails: Software-Exploitable Hardware Bugs.
CoRR, 2018

2017
Did we learn from LLC Side Channel Attacks? A Cache Leakage Detection Tool for Crypto Libraries.
CoRR, 2017

2016
Controlling your control flow graph.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

2015
MAGIC: Malicious Aging in Circuits/Cores.
ACM Trans. Archit. Code Optim., 2015

Reliable Integrity Checking in Multicore Processors.
ACM Trans. Archit. Code Optim., 2015

2013
Securing Processors Against Insider Attacks: A Circuit-Microarchitecture Co-Design Approach.
IEEE Des. Test, 2013

Hardware and embedded security in the context of internet of things.
Proceedings of the CyCAR'13, 2013

2012
Architecture Support for Dynamic Integrity Checking.
IEEE Trans. Inf. Forensics Secur., 2012

A Survey of Microarchitecture Support for Embedded Processor Security.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

A high-performance, low-overhead microarchitecture for secure program execution.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2010
Feasibility study of dynamic Trusted Platform Module.
Proceedings of the 28th International Conference on Computer Design, 2010


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