Mohammad Riazati

According to our database1, Mohammad Riazati authored at least 13 papers between 2006 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
DeepKit: a multistage exploration framework for hardware implementation of deep learning.
PhD thesis, 2023

DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

2022
DeepFlexiHLS: Deep Neural Network Flexible High-Level Synthesis Directive Generator.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, 2022

TAS: Ternarized Neural Architecture Search for Resource-Constrained Edge Devices.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

AutoDeepHLS: Deep Neural Network High-level Synthesis using fixed-point precision.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2020
DeepHLS: A complete toolchain for automatic synthesis of deep neural networks to FPGA.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

Adjustable self-healing methodology for accelerated functions in heterogeneous systems.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

SHiLA: Synthesizing High-Level Assertions for High-Speed Validation of High-Level Designs.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

2019
An incentive mechanism to promote honesty among seller agents in electronic marketplaces.
Electron. Commer. Res., 2019

2008
Enhancing the Testability of RTL Designs Using Efficiently Synthesized Assertions.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
Distributing Congestions in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006
Low-power multiplier with static decision for input manipulation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006


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