Mohammad Reza Kakoee

Valeria Bertacco

IEEE Trans. Computers, 2014

2013

A shared-FPU architecture for ultra-low power MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the Computing Frontiers Conference, 2013

2012

Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2012

Robust Near-Threshold Design With Fine-Grained Performance Tunability.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Row-based FBB: A design-time optimization for post-silicon tunable circuits.

[BibT_eX]

[DOI]

Ashoka Visweswara Sathanur

Antonio Pullini

Microelectron. J., 2012

Evaluation of GALS Methods in Scaled CMOS Technology: Moonrake Chip Experience.

[BibT_eX]

[DOI]

Int. J. Embed. Real Time Commun. Syst., 2012

A tightly-coupled multi-core cluster with shared-memory HW accelerators.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

A multi-banked shared-l1 cache architecture for tightly coupled processor clusters.

[BibT_eX]

[DOI]

Vladimir Petrovic

Proceedings of the 2012 International Symposium on System on Chip, 2012

A resilient architecture for low latency communication in shared-L1 processor clusters.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph.

[BibT_eX]

[DOI]

Mohammad Hosseinabady

Jimson Mathew

Dhiraj K. Pradhan

IEEE Trans. Very Large Scale Integr. Syst., 2011

Fine-Grained Power and Body-Bias Control for Near-Threshold Deep Sub-Micron CMOS Circuits.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

A distributed and topology-agnostic approach for on-line NoC testing.

[BibT_eX]

[DOI]

Valeria Bertacco

Proceedings of the NOCS 2011, 2011

Moonrake chip - GALS demonstrator in 40 nm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Symposium on System on Chip, 2011

A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

ReliNoC: A reliable network for priority-based on-chip communication.

[BibT_eX]

[DOI]

Valeria Bertacco

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Automatic synthesis of near-threshold circuits with fine-grained performance tunability.

[BibT_eX]

[DOI]

Ashoka Visweswara Sathanur

Antonio Pullini

Jos Huisken

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

A new physical routing approach for robust bundled signaling on NoC links.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009

A floorplan-aware interactive tool flow for NoC design and synthesis.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

2008

Graph based test case generation for TLM functional verification.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2008

Enhancing the Testability of RTL Designs Using Efficiently Synthesized Assertions.

[BibT_eX]

[DOI]

Mohammad Riazati

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification.

[BibT_eX]

[DOI]

Mohammad Riazati

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs.

[BibT_eX]

[DOI]

Mohammad Hosseinabady

Jimson Mathew

Dhiraj K. Pradhan

Proceedings of the Design, Automation and Test in Europe, 2008

2007

HW/SW architecture for soft-error cancellation in real-time operating system.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2007

Assertion based design error diagnosis for core-based SoCs.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International SOC Conference, 2007

A New Approach for Design and Verification of Transaction Level Models.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Reliable network-on-chip based on generalized de Bruijn graph.

[BibT_eX]

[DOI]

Mohammad Hosseinabady

Jimson Mathew

Dhiraj K. Pradhan

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

Functional Test-Case Generation by a Control Transaction Graph for TLM Verification.

[BibT_eX]

[DOI]

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

On-Chip Verification of NoCs Using Assertion Processors.

[BibT_eX]

[DOI]

Zainalabedin Navabi

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Improving Robustness of Real-Time Operating Systems (RTOS) Services Related to Soft-Errors.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2007), 2007

2006

Modified Pseudo LRU Replacement Algorithm.

[BibT_eX]

[DOI]

Hassan Ghasemzadeh

Sepideh Mazrouee

Proceedings of the 13th Annual IEEE International Conference and Workshop on Engineering of Computer Based Systems (ECBS 2006), 2006

2003

Using Integer Equations for High Level Formal Verification Property Checking.

[BibT_eX]

[DOI]

Bijan Alizadeh