Mohammad Hossein Neishaburi

According to our database, Mohammad Hossein Neishaburi authored at least 26 papers between 2007 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

System on chip failure rate assessment using the executable model of a system.

Mohammad Hossein Neishaburi, Zeljko Zilic

Computing, 2015

2014

On a New Mechanism of Trigger Generation for Post-Silicon Debugging.

Mohammad Hossein Neishaburi, Zeljko Zilic

IEEE Trans. Computers, 2014

2013

NISHA: A fault-tolerant NoC router enabling deadlock-free Interconnection of Subnets in Hierarchical Architectures.

Mohammad Hossein Neishaburi, Zeljko Zilic

J. Syst. Archit., 2013

A Fault Tolerant Hierarchical Network on Chip Router Architecture.

Mohammad Hossein Neishaburi, Zeljko Zilic

J. Electron. Test., 2013

2012

An infrastructure for debug using clusters of assertion-checkers.

Mohammad Hossein Neishaburi, Zeljko Zilic

Microelectron. Reliab., 2012

An enhanced debug-aware network interface for Network-on-Chip.

Mohammad Hossein Neishaburi, Zeljko Zilic

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011

A distributed AXI-based platform for post-silicon validation.

Mohammad Hossein Neishaburi, Zeljko Zilic

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

ERAVC: Enhanced reliability aware NoC router.

Mohammad Hossein Neishaburi, Zeljko Zilic

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

On Failure Rate Assessment Using an Executable Model of the System.

Mohammad Hossein Neishaburi, Zeljko Zilic

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Debug Aware AXI-based Network Interface.

Mohammad Hossein Neishaburi, Zeljko Zilic

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Hierarchical Embedded Logic Analyzer for Accurate Root-Cause Analysis.

Mohammad Hossein Neishaburi, Zeljko Zilic

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

2010

Enabling efficient post-silicon debug by clustering of hardware-assertions.

Mohammad Hossein Neishaburi, Zeljko Zilic

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Reliability aware NoC router architecture using input channel buffer sharing.

Mohammad Hossein Neishaburi, Zeljko Zilic

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

An efficent dynamic multicast routing protocol for distributing traffic in NOCs.

Masoumeh Ebrahimi, Masoud Daneshtalab, Mohammad Hossein Neishaburi, Siamak Mohammadi, Ali Afzali-Kusha, Juha Plosila, Hannu Tenhunen

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Graph based test case generation for TLM functional verification.

Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi

Microprocess. Microsystems, 2008

2007

HW/SW architecture for soft-error cancellation in real-time operating system.

Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari

IEICE Electron. Express, 2007

A UML Based System Level Failure Rate Assessment Technique for SoC Designs.

Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Distributing Congestions in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections.

Masoud Daneshtalab, A. Pedram, Mohammad Hossein Neishaburi, Mohammad Riazati, Ali Afzali-Kusha, Siamak Mohammadi

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Assertion based design error diagnosis for core-based SoCs.

Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari

Proceedings of the 2007 IEEE International SOC Conference, 2007

Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC.

Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Functional Test-Case Generation by a Control Transaction Graph for TLM Verification.

Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

On-Chip Verification of NoCs Using Assertion Processors.

Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services.

Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

System Level Voltage Scheduling Technique Using UML-RT Model.

Mohammad Hossein Neishaburi, Masoud Daneshtalab, Majid Nabi, Siamak Mohammadi

Proceedings of the 2007 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2007), 2007

Improving Robustness of Real-Time Operating Systems (RTOS) Services Related to Soft-Errors.

Mohammad Hossein Neishaburi, Masoud Daneshtalab, Mohammad Reza Kakoee, Saeed Safari

Proceedings of the 2007 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2007), 2007

A Superior Low Complexity Rate Control Algorithm.

Alireza Aminlou, Maryam Homayouni, Mohammad Hossein Neishaburi, Siamak Mohammadi

Proceedings of the 2007 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2007), 2007