Mojtaba Valinataj

According to our database, Mojtaba Valinataj authored at least 21 papers between 2007 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

High-speed binary coded decimal digit multipliers with multiple error detection.

Zahra Yazdanian Amiri, Mojtaba Valinataj

Integr., November, 2023

2022

Hierarchical multipliers: A framework for high-speed multiple error detecting architectures.

Mojtaba Valinataj, Axel Jantsch

Microelectron. J., 2022

Operational Conditions Analysis for Memristive Stateful Logics - A Study on IMPLY and TMSL.

Roya Rahimi Disfani, Nima TaheriNejad, Mojtaba Valinataj

Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

2021

Comments on "Improved designs of digit-by-digit decimal multiplier".

Mojtaba Valinataj, Zahra Yazdanian Amiri

Integr., 2021

High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic.

Maytham Allahi Rudposhti, Mojtaba Valinataj

Integr., 2021

2019

Parloom: A New Low-Power Set-Associative Instruction Cache Architecture Utilizing Enhanced Counting Bloom Filter and Partial Tags.

Sajjad Rostami Sani, Mojtaba Valinataj, Saeideh Alinezhad Chamazcoti

J. Circuits Syst. Comput., 2019

2018

A low-cost high-speed self-checking carry select adder with multiple-fault detection.

Mojtaba Valinataj, Abbas Mohammadnezhad, Jari Nurmi

Microelectron. J., 2018

aPaRT: A Fast Meta-Heuristic Algorithm using Path-Relinking and Tabu Search for Allocating Machines to Operations in FJSP Problem.

Hamid Jazayeriy, Sahar Bakhtar, Mojtaba Valinataj

Inteligencia Artif., 2018

2017

Novel parity-preserving reversible logic array multipliers.

Mojtaba Valinataj

J. Supercomput., 2017

2016

A low-cost, fault-tolerant and high-performance router architecture for on-chip networks.

Mojtaba Valinataj, Mostafa Shahiri

Microprocess. Microsystems, 2016

Novel low-cost and fault-tolerant reversible logic adders.

Mojtaba Valinataj, Mahboobeh Mirshekar, Hamid Jazayeri

Comput. Electr. Eng., 2016

A reliable and high-performance Network-on-Chip router through decoupled resource sharing.

Mostafa Shahiri, Mojtaba Valinataj, Amir M. Rahmani

Proceedings of the International Conference on High Performance Computing & Simulation, 2016

2015

Fault-tolerant carry look-ahead adder architectures robust to multiple simultaneous errors.

Mojtaba Valinataj

Microelectron. Reliab., 2015

2014

A novel self-checking carry lookahead adder with multiple error detection/correction.

Mojtaba Valinataj

Microprocess. Microsystems, 2014

2013

Enhanced fault-tolerant Network-on-Chip architecture using hierarchical agents.

Mojtaba Valinataj, Pasi Liljeberg, Juha Plosila

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2011

A fault-tolerant and hierarchical routing algorithm for NoC architectures.

Mojtaba Valinataj, Pasi Liljeberg, Juha Plosila

Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

Evaluation of Fault-Tolerant Routing Methods for NoC Architectures.

Mojtaba Valinataj

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010

A fault-aware, reconfigurable and adaptive routing algorithm for NoC applications.

Mojtaba Valinataj, Siamak Mohammadi

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

A fault-tolerant and congestion-aware routing algorithm for Networks-on-Chip.

Mojtaba Valinataj, Siamak Mohammadi, Juha Plosila, Pasi Liljeberg

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2008

Inherent reliability evaluation of Networks-on-Chip based on analytical models.

Mojtaba Valinataj, Siamak Mohammadi, Saeed Safari

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

2007

Fault Tolerant Arithmetic Operations with Multiple Error Detection and Correction.

Mojtaba Valinataj, Saeed Safari

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007