Saeideh Alinezhad Chamazcoti

Orcid: 0000-0002-0097-6375

According to our database1, Saeideh Alinezhad Chamazcoti authored at least 9 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Other 

Links

On csauthors.net:

Bibliography

2023
Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023

Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
Design exploration of IGZO diode based VCMA array design for Storage Class Memory Applications.
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022

2019
Can Erasure Codes Damage Reliability in SSD-Based Storage Systems?
IEEE Trans. Emerg. Top. Comput., 2019

Parloom: A New Low-Power Set-Associative Instruction Cache Architecture Utilizing Enhanced Counting Bloom Filter and Partial Tags.
J. Circuits Syst. Comput., 2019

2017
Hybrid RAID: A Solution for Enhancing the Reliability of SSD-Based RAIDs.
IEEE Trans. Multi Scale Comput. Syst., 2017

2016
On designing endurance aware erasure code for SSD-based storage systems.
Microprocess. Microsystems, 2016

2015
On endurance and performance of erasure codes in SSD-based storage systems.
Microelectron. Reliab., 2015

2014
EA-EO: Endurance Aware Erasure Code for SSD-Based Storage Systems.
Proceedings of the 20th IEEE Pacific Rim International Symposium on Dependable Computing, 2014


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