Mu-Tien Chang

According to our database, Mu-Tien Chang authored at least 11 papers between 2007 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Performance Impact of Emerging Memory Technologies on Big Data Applications: A Latency-Programmable System Emulation Approach.

Mu-Tien Chang, I. Stephen Choi, Dimin Niu, Hongzhong Zheng

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017

Architecting HBM as a high bandwidth, high capacity, self-managed last-level cache.

Tyler Stocksdale, Mu-Tien Chang, Hongzhong Zheng, Frank Mueller

Proceedings of the 2nd Joint International Workshop on Parallel Data Storage & Data Intensive Scalable Computing Systems, 2017

FlashStorageSim: Performance Modeling for SSD Architectures.

Krishna T. Malladi, Mu-Tien Chang, Dimin Niu, Hongzhong Zheng

Proceedings of the 2017 International Conference on Networking, Architecture, and Storage, 2017

2016

DRAM Refresh Mechanisms, Penalties, and Trade-Offs.

Ishwar Bhati, Mu-Tien Chang, Zeshan Chishti, Shih-Lien Lu, Bruce L. Jacob

IEEE Trans. Computers, 2016

2015

FAME: A Fast and Accurate Memory Emulator for New Memory System Architecture Exploration.

Krishna T. Malladi, Mu-Tien Chang, John Ping, Hongzhong Zheng

Proceedings of the 23rd IEEE International Symposium on Modeling, 2015

2013

Technology comparison for large last-level caches (L³Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM.

Mu-Tien Chang, Paul Rosenfeld, Shih-Lien Lu, Bruce L. Jacob

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012

Energy-Efficient Cached DIMM Architecture.

Mu-Tien Chang, Joe Gross, Bruce L. Jacob

Proceedings of the 20th IEEE International Symposium on Modeling, 2012

2011

An analytical model to estimate PCM failure probability due to process variations.

Mu-Tien Chang, Bruce L. Jacob

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

2008

A robust ultra-low power asynchronous FIFO memory with self-adaptive power control.

Mu-Tien Chang, Po-Tsang Huang, Wei Hwang

Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

A fully-differential subthreshold SRAM cell with auto-compensation.

Mu-Tien Chang, Wei Hwang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

A 65nm low power 2T1D embedded DRAM with leakage current reduction.

Mu-Tien Chang, Po-Tsang Huang, Wei Hwang

Proceedings of the 2007 IEEE International SOC Conference, 2007