Mukesh Agrawal

According to our database, Mukesh Agrawal authored at least 13 papers between 2012 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

Micro-Sector Cache: Improving Space Utilization in Sectored DRAM Caches.

Mainak Chaudhuri, Mukesh Agrawal, Jayesh Gaur, Sreenivas Subramoney

ACM Trans. Archit. Code Optim., 2017

2016

A Distributed, Reconfigurable, and Reusable BIST Infrastructure for Test and Diagnosis of 3-D-Stacked ICs.

Mukesh Agrawal, Krishnendu Chakrabarty, Bill Eklow

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

The hype, myths, and realities of testing 3D integrated circuits.

Ran Wang, Sergej Deutsch, Mukesh Agrawal, Krishnendu Chakrabarty

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015

Reuse-Based Optimization for Prebond and Post-Bond Testing of 3-D-Stacked ICs.

Mukesh Agrawal, Krishnendu Chakrabarty, Randy Widialaksono

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Test-Cost Modeling and Optimal Test-Flow Selection of 3-D-Stacked ICs.

Mukesh Agrawal, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2014

Optimization of Test and Design-for-Testability Solutions for Many-Core System-on-Chip Designs.

Mukesh Agrawal

PhD thesis, 2014

Test-Delivery Optimization in Manycore SOCs.

Mukesh Agrawal, Michael Richter, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Test and Design-for-Testability Solutions for 3D Integrated Circuits.

Krishnendu Chakrabarty, Mukesh Agrawal, Sergej Deutsch, Brandon Noia, Ran Wang, Fangming Ye

IPSJ Trans. Syst. LSI Des. Methodol., 2014

Test-time optimization in NOC-based manycore SOCs using multicast routing.

Mukesh Agrawal, Krishnendu Chakrabarty

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

A distributed, reconfigurable, and reusable bist infrastructure for 3D-stacked ICs.

Mukesh Agrawal, Krishnendu Chakrabarty, Bill Eklow

Proceedings of the 2014 International Test Conference, 2014

2013

Test-cost optimization and test-flow selection for 3D-stacked ICs.

Mukesh Agrawal, Krishnendu Chakrabarty

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

A graph-theoretic approach for minimizing the number of wrapper cells for pre-bond testing of 3D-stacked ICs.

Mukesh Agrawal, Krishnendu Chakrabarty

Proceedings of the 2013 IEEE International Test Conference, 2013

2012

A dynamic programming solution for optimizing test delivery in multicore SOCs.

Mukesh Agrawal, Michael Richter, Krishnendu Chakrabarty

Proceedings of the 2012 IEEE International Test Conference, 2012