Jayesh Gaur

According to our database1, Jayesh Gaur authored at least 19 papers between 2007 and 2024.

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Bibliography

2024
Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

2022
Speculative Code Compaction: Eliminating Dead Code via Speculative Microcode Transformations.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Register file prefetching.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

2021
Cryptographic Capability Computing.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Stream Floating: Enabling Proactive and Decentralized Cache Optimizations.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

2020
Auto-Predication of Critical Branches.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Focused Value Prediction.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

2019
Post-silicon CPU adaptation made practical using machine learning.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

Bandwidth-Aware Last-Level Caching: Efficiently Coordinating Off-Chip Read and Write Bandwidth.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

2018
MARS: Memory Aware Reordered Source.
CoRR, 2018

Criticality Aware Tiered Cache Hierarchy: A Fundamental Relook at Multi-Level Cache Hierarchies.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

2017
Micro-Sector Cache: Improving Space Utilization in Sectored DRAM Caches.
ACM Trans. Archit. Code Optim., 2017

Near-Optimal Access Partitioning for Memory Hierarchies with Multiple Heterogeneous Bandwidth Sources.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

2016
Base-Victim Compression: An Opportunistic Cache Compression Architecture.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

2013
Efficient management of last-level caches in graphics processors for 3D scene rendering workloads.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

2012
Introducing hierarchy-awareness in replacement and bypass algorithms for last-level caches.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
Bypass and insertion algorithms for exclusive last-level caches.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

2007
Leveraging Semi-Formal and Sequential Equivalence Techniques for Multimedia SOC Performance Validation.
Proceedings of the 44th Design Automation Conference, 2007


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