Ran Wang

According to our database, Ran Wang authored at least 27 papers between 2013 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Intrinsic Security: A Robust Framework for Cloud-Native Network Slicing via a Proactive Defense Paradigm.

Qiang Wu, Ran Wang, Xincheng Yan, Chunming Wu, Rongxing Lu

IEEE Wirel. Commun., 2022

2021

GACDN: generative adversarial feature completion and diagnosis network for COVID-19.

Qi Zhu, Haizhou Ye, Liang Sun, Zhongnian Li, Ran Wang, Feng Shi, Dinggang Shen, Daoqiang Zhang

BMC Medical Imaging, 2021

2020

Cross-spectral palmprint recognition with low-rank canonical correlation analysis.

Qi Zhu, Nuoya Xu, Zheng Zhang, Donghai Guan, Ran Wang, Daoqiang Zhang

Multim. Tools Appl., 2020

2018

Multicast Testing of Interposer-Based 2.5D ICs: Test-Architecture Design and Test Scheduling.

Shengcheng Wang, Ran Wang, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori

ACM Trans. Design Autom. Electr. Syst., 2018

Visible Light Based Occupancy Inference Using Ensemble Learning.

Jie Hao, Xiaoming Yuan, Yanbing Yang, Ran Wang, Yi Zhuang, Jun Luo

IEEE Access, 2018

A Collective Computing Architecture Supporting Heterogeneous Tasks and Computing Devices.

Yang Li, Yunlong Zhao, Zhenhua Zhang, Qian Geng, Ran Wang

Proceedings of the Cloud Computing and Security - 4th International Conference, 2018

A Flexible Network Utility Optimization Approach for Energy Harvesting Sensor Networks.

Jie Hao, Ran Wang, Yi Zhuang, Baoxian Zhang

Proceedings of the IEEE Global Communications Conference, 2018

2017

ExTest Scheduling and Optimization for 2.5-D SoCs With Wrapped Tiles.

Ran Wang, Guoliang Li, Rui Li, Jun Qian, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Prebond Testing and Test-Path Design for the Silicon Interposer in 2.5-D ICs.

Ran Wang, Zipeng Li, Sukeshwar Kannan, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Tackling Test Challenges for Interposer-Based 2.5-D Integrated Circuits.

Ran Wang, Krishnendu Chakrabarty

IEEE Des. Test, 2017

2016

Testing of Interposer-Based 2.5D Integrated Circuits.

Ran Wang

PhD thesis, 2016

A programmable method for low-power scan shift in SoC integrated circuits.

Ran Wang, Bonita Bhaskaran, Karthikeyan Natarajan, Ayub Abdollahian, Kaushik Narayanun, Krishnendu Chakrabarty, Amit Sanghani

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Testing of interposer-based 2.5D integrated circuits.

Ran Wang, Krishnendu Chakrabarty

Proceedings of the 2016 IEEE International Test Conference, 2016

The hype, myths, and realities of testing 3D integrated circuits.

Ran Wang, Sergej Deutsch, Mukesh Agrawal, Krishnendu Chakrabarty

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

A design-for-test solution for monolithic 3D integrated circuits.

Ran Wang, Krishnendu Chakrabarty

Proceedings of the 21th IEEE European Test Symposium, 2016

Pre-bond testing of the silicon interposer in 2.5D ICs.

Ran Wang, Zipeng Li, Sukeshwar Kannan, Krishnendu Chakrabarty

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Multicast Test Architecture and Test Scheduling for Interposer-Based 2.5D ICs.

Shengcheng Wang, Ran Wang, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori

Proceedings of the 25th IEEE Asian Test Symposium, 2016

Testing of Interposer-Based 2.5D Integrated Circuits: Challenges and Solutions.

Ran Wang, Krishnendu Chakrabarty

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

Built-In Self-Test and Test Scheduling for Interposer-Based 2.5D IC.

Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik

ACM Trans. Design Autom. Electr. Syst., 2015

Interconnect Testing and Test-Path Scheduling for Interposer-Based 2.5-D ICs.

Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

ExTest scheduling for 2.5D system-on-chip integrated circuits.

Ran Wang, Guoliang Li, Rui Li, Jun Qian, Krishnendu Chakrabarty

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

2014

Built-In Self-Test, Diagnosis, and Repair of MultiMode Power Switches.

Ran Wang, Zhaobo Zhang, Xrysovalantis Kavousianos, Yiorgos Tsiatouhas, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Scan-Based Testing of Post-Bond Silicon Interposer Interconnects in 2.5-D ICs.

Ran Wang, Krishnendu Chakrabarty, Bill Eklow

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Test and Design-for-Testability Solutions for 3D Integrated Circuits.

Krishnendu Chakrabarty, Mukesh Agrawal, Sergej Deutsch, Brandon Noia, Ran Wang, Fangming Ye

IPSJ Trans. Syst. LSI Des. Methodol., 2014

At-speed interconnect testing and test-path optimization for 2.5D ICs.

Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Built-in self-test for interposer-based 2.5D ICs.

Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013

Post-bond Testing of the Silicon Interposer and Micro-bumps in 2.5D ICs.

Ran Wang, Krishnendu Chakrabarty, Bill Eklow

Proceedings of the 22nd Asian Test Symposium, 2013