N. P. van der Meijs

According to our database, N. P. van der Meijs authored at least 44 papers between 1984 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

Dynamic Thermal Estimation Methodology for High-Performance 3-D MPSoC.

Amir Zjajo, Nick van der Meijs, Rene van Leuken

IEEE Trans. Very Large Scale Integr. Syst., 2014

Considering Crosstalk Effects in Statistical Timing Analysis.

Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver.

Qin Tang, Javier Rodríguez, Amir Zjajo, Michel Berkelaar, Nick van der Meijs

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Statistical power optimization of deep-submicron digital CMOS circuits based on structured perceptron.

Amir Zjajo, Nick van der Meijs, Rene van Leuken

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

A 0.1pJ Freeze Vernier time-to-digital converter in 65nm CMOS.

Kristof Blutman, Jan A. Angevare, Amir Zjajo, Nick van der Meijs

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Adaptive Thermal Monitoring of Deep-Submicron CMOS VLSI Circuits.

Amir Zjajo, Nick van der Meijs, Rene van Leuken

J. Low Power Electron., 2013

A CMOS 0.23pj Freeze Vernier Time-To-Digital Converter.

Jan A. Angevare, Kristof Blutman, Amir Zjajo, Nick van der Meijs

Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013

Balanced stochastic truncation of coupled 3D interconnect.

Amir Zjajo, Nick van der Meijs, Rene van Leuken

Proceedings of 2013 International Conference on IC Design & Technology, 2013

2012

Direct Statistical Simulation of Timing Properties in Sequential Circuits.

Javier Rodríguez, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

Thermal analysis of 3D integrated circuits based on discontinuous Galerkin finite element method.

Amir Zjajo, Nick van der Meijs, Rene van Leuken

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

A 11 µW 0°C-160°C temperature sensor in 90 nm CMOS for adaptive thermal monitoring of VLSI circuits.

Amir Zjajo, Nick van der Meijs, René van Leuken

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Transistor-level gate model based statistical timing analysis considering correlations.

Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Crosstalk-aware statistical interconnect delay calculation.

Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs.

Amir Zjajo, Qin Tang, Michel Berkelaar, José Pineda de Gyvez, Alessandro Di Bucchianico, Nick van der Meijs

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A 26 μ W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios.

Pieter Harpe, Cui Zhou, Yu Bi, N. P. van der Meijs, Xiaoyan Wang, Kathleen Philips, Guido Dolmans, Harmke de Groot

IEEE J. Solid State Circuits, 2011

Pseudo circuit model for representing uncertainty in waveforms.

Ashish Nigam, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs

Proceedings of the Design, Automation and Test in Europe, 2011

Fast statistical analysis of RC nets subject to manufacturing variabilities.

Yu Bi, Kees-Jan van der Kolk, Jorge Fernandez Villena, Luís Miguel Silveira, Nick van der Meijs

Proceedings of the Design, Automation and Test in Europe, 2011

Enhanced sensitivity computation for BEM based capacitance extraction using the Schur complement technique.

Yu Bi, Simon de Graaf, Nick van der Meijs

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Efficient sensitivity-based capacitance modeling for systematic and random geometric variations.

Yu Bi, Pieter Harpe, N. P. van der Meijs

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Statistical Moment Estimation of Delay and Power in Circuit Simulation.

Ashish Nigam, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs

J. Low Power Electron., 2010

Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations.

Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

Digital cartesian feedback linearization of switched mode power amplifiers.

Alejandro Viteri, Amir Zjajo, Thijmen Hamoen, Nick van der Meijs

Proceedings of the 17th IEEE International Conference on Electronics, 2010

RDE-based transistor-level gate simulation for statistical static timing analysis.

Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs

Proceedings of the 47th Design Automation Conference, 2010

Noise analysis of non-linear dynamic integrated circuits.

Amir Zjajo, Qin Tang, Michel Berkelaar, Nick van der Meijs

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

A Radix 2² based parallel pipeline FFT processor for MB-OFDM UWB system.

Nuo Li, Nick van der Meijs

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Sensitivity computation using domain-decomposition for boundary element method based capacitance extractors.

Yu Bi, Kees-Jan van der Kolk, Nick van der Meijs

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2004

Statistically Aware Buffer Planning.

Giuseppe S. Garcea, N. P. van der Meijs, Kees-Jan van der Kolk, Ralph H. J. M. Otten

Proceedings of the 2004 Design, 2004

2003

Simultaneous Analytic Area and Power Optimization for Repeater Insertion.

Giuseppe S. Garcea, N. P. van der Meijs, Ralph H. J. M. Otten

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Analytic model for area and power constrained optimal repeater insertion.

Giuseppe S. Garcea, Nick van der Meijs, Ralph H. J. M. Otten

Proceedings of the ESSCIRC 2003, 2003

2002

Theoretical and practical validation of combined BEM/FEM substrate resistance modeling.

Eelco Schrik, Patrick M. Dewilde, N. P. van der Meijs

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Combined BEM/FEM substrate resistance modeling.

Eelco Schrik, N. P. van der Meijs

Proceedings of the 39th Design Automation Conference, 2002

1999

Virtual screening: a step towards a sparse partial inductance matrix.

A. J. Dammers, N. P. van der Meijs

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1997

Cartesian multipole based numerical integration for 3D capacitance extraction.

U. Geigenmüller, N. P. van der Meijs

Proceedings of the European Design and Test Conference, 1997

1996

Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits.

N. P. van der Meijs, T. Smedes

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Fast Computation of Substrate Resistances in Large Circuits.

Arjan J. van Genderen, N. P. van der Meijs, T. Smedes

Proceedings of the 1996 European Design and Test Conference, 1996

Including Higher-Order Moments of RC Interconnections in Layout-to-Circuit Extraction.

P. J. H. Elias, N. P. van der Meijs

Proceedings of the 1996 European Design and Test Conference, 1996

Using Articulation Nodes to Improve the Efficiency of Finite-Element based Resistance Extraction.

Arjan J. van Genderen, N. P. van der Meijs

Proceedings of the 33st Conference on Design Automation, 1996

Extracting Circuit Models for Large RC Interconnections that are Accurate up to a Predefined Signal Frequency.

P. J. H. Elias, N. P. van der Meijs

Proceedings of the 33st Conference on Design Automation, 1996

1995

Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits.

Frederik Beeftink, Arjan J. van Genderen, N. P. van der Meijs

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Extraction of circuit models for substrate cross-talk.

T. Smedes, N. P. van der Meijs, Arjan J. van Genderen

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Delayed Frontal Solution for Finite-Element Based Resistance Extraction.

N. P. van der Meijs, Arjan J. van Genderen

Proceedings of the 32st Conference on Design Automation, 1995

1993

Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures.

Arjan J. van Genderen, N. P. van der Meijs

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1989

An Efficient Finite Element Method for Submicron IC Capacitance Extraction.

N. P. van der Meijs, Arjan J. van Genderen

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1984

VLSI circuit reconstruction from mask topology.

N. P. van der Meijs, J. T. Fokkema

Integr., 1984