Luís Miguel Silveira

Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021

2019

Reduced order models of myelinated axonal compartments.

[BibT_eX]

[DOI]

J. Comput. Neurosci., 2019

2018

Micro-VMS: A VMS Mobile Unit for Artisanal Fishing Vessels.

[BibT_eX]

[DOI]

Pedro Lousã

Fernando Moreira

Proceedings of the 16th International Conference on Intelligent Transportation Systems Telecommunications, 2018

2017

Circuit Synthesis for Guaranteed Positive Sparse Realization of Passive State-Space Models.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Improved 7 Tesla resting-state fMRI connectivity measurements by cluster-based modeling of respiratory volume and heart rate effects.

[BibT_eX]

[DOI]

NeuroImage, 2017

2016

Physiological noise model comparison for resting-state fMRI at 7 T.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Biomedical Imaging, 2016

Variability and statistical analysis flow for dynamic linear systems with large number of inputs.

[BibT_eX]

[DOI]

A. Lucas Martins

Alexandre Paulo Francisco

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

A new hierarchical brain parcellation method based on discrete morse theory for functional MRI data.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Symposium on Biomedical Imaging, 2015

Techniques for Brain Functional Connectivity Analysis from High Resolution Imaging.

[BibT_eX]

[DOI]

A. C. Leitão

Proceedings of the Complex Networks VI, 2015

2014

Efficient analysis of variability impact on interconnect lines and resistor networks.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Improving SAT Solver Efficiency Using a Multi-Core Approach.

[BibT_eX]

[DOI]

Proceedings of the Twenty-Sixth International Florida Artificial Intelligence Research Society Conference, 2013

2012

Exploiting Parallelism for Improved Automation of Multidimensional Model Order Reduction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2011

Multi-Dimensional Automatic Sampling Schemes for Multi-Point Modeling Methodologies.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Positive realization of reduced RLCM nets.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Handling intra-die variations in PSTA.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Fast statistical analysis of RC nets subject to manufacturing variabilities.

[BibT_eX]

[DOI]

Yu Bi

Kees-Jan van der Kolk

Nick van der Meijs

Proceedings of the Design, Automation and Test in Europe, 2011

2010

SPARE - A Scalable Algorithm for Passive, Structure Preserving, Parameter-Aware Model Order Reduction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Efficient Simulation of Power Grids.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Effective Corner-Based Techniques for Variation-Aware IC Timing Verification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

3POr - Parallel projection based parameterized order reduction for multi-dimensional linear models.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Extended Hamiltonian Pencil for passivity assessment and enforcement for S-parameter systems.

[BibT_eX]

[DOI]

Zuochang Ye

Proceedings of the Design, Automation and Test in Europe, 2010

HORUS - high-dimensional Model Order Reduction via low moment-matching upgraded sampling.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Speedpath analysis under parametric timing models.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

2009

Generating realistic stimuli for accurate power grid analysis.

[BibT_eX]

[DOI]

Pedro Marques Morgado

Paulo F. Flores

ACM Trans. Design Autom. Electr. Syst., 2009

PMSat: a parallel version of MiniSAT.

[BibT_eX]

[DOI]

Luís Gil

Paulo F. Flores

J. Satisf. Boolean Model. Comput., 2009

Power Macro-Modeling Using an Iterative LS-SVM Method.

[BibT_eX]

[DOI]

António Gusmão

José Monteiro

Proceedings of the VLSI-SoC: Technologies for Systems Integration, 2009

Parameter tuning in SVM-based power macro-modeling.

[BibT_eX]

[DOI]

António Gusmão

José Monteiro

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Fast and reliable passivity assessment and enforcement with extended Hamiltonian pencil.

[BibT_eX]

[DOI]

Zuochang Ye

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

On the efficient reduction of complete EM based parametric models.

[BibT_eX]

[DOI]

Gabriela Ciuprina

Daniel Ioan

Proceedings of the Design, Automation and Test in Europe, 2009

ARMS - automatic residue-minimization based sampling for multi-point modeling techniques.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

Generating Worst-Case Stimuli for Accurate Power Grid Analysis.

[BibT_eX]

[DOI]

Pedro Marques Morgado

Paulo F. Flores

José C. Monteiro

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Efficient Representation and Analysis of Power Grids.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Substrate model extraction using finite differences and parallel multigrid.

[BibT_eX]

[DOI]

Integr., 2007

Dynamic models for substrate coupling in mixed-mode systems.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2007

Parametric Structure-Preserving Model Order Reduction.

[BibT_eX]

[DOI]

Wil H. A. Schilders

Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007

On the Compressibility of Power Grid Models.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

On the Effectiveness of Reducing Large Linear Networks with Many Ports.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Efficient computation of the worst-delay corner.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Generating High-Accuracy Simulation Models Using Problem-Tailored Orthogonal Polynomials Basis.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Resampling Plans for Sample Point Selection in Multipoint Model-Order Reduction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Library Compatible Variational Delay Computation.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

Variation-Aware, Library Compatible Delay Modeling Strategy.

[BibT_eX]

[DOI]

Proceedings of the IFIP VLSI-SoC 2006, 2006

2005

Poor man's TBR: a simple model reduction scheme.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Issues in Model Reduction of Power Grids.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Grid-based statistical timing analysis.

[BibT_eX]

Proceedings of the AC 2005, 2005

2004

A convex programming approach for generating guaranteed passive approximations to tabulated frequency-data.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Power Estimation Using Probability Polynomials.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2004

Issues in parallelizing multigrid-based substrate model extraction and analysis.

[BibT_eX]

[DOI]

Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Multigrid-based substrate coupling model extraction.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Exploiting input information in a model reduction algorithm for massively coupled parasitic networks.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

2003

Guaranteed passive balancing transformations for model order reduction.

[BibT_eX]

[DOI]

Luca Daniel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Analog Macromodeling using Kernel Methods.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002

Satisfiability models and algorithms for circuit delay computation.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2002

Characterizing Substrate Coupling in Deep-Submicron Designs.

[BibT_eX]

[DOI]

Nuno Vargas

IEEE Des. Test Comput., 2002

On Generating Compact, Passive Models of Frequency-Described Systems.

[BibT_eX]

[DOI]

Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

Optimization based passive constrained fitting.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Passive Constrained Rational Approximation Algorithm Using Nevanlinna-Pick Interpolation.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

2001

Simulation Approaches for Strongly Coupled Interconnect Systems.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

A Convex Programming Approach to Positive Real Rational Approximation.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

2000

A benchmark suite for substrate analysis.

[BibT_eX]

[DOI]

Edoardo Charbon

Paolo Miliozzi

Proceedings of ASP-DAC 2000, 2000

1999

Efficient techniques for accurate modeling and simulation ofsubstrate coupling in mixed-signal IC's.

[BibT_eX]

[DOI]

João Paulo Costa

Mike Chou

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Improving the efficiency of parasitic extraction and simulation of 3D interconnect models.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

A probabilistic approach for RT-level power modeling.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Algorithms for Solving Boolean Satisfiability in Combinational Circuits.

[BibT_eX]

[DOI]

João Marques-Silva

Proceedings of the 1999 Design, 1999

Efficient Techniques for Accurate Extraction and Modeling of Substrate Coupling in Mixed-Signal IC's.

[BibT_eX]

[DOI]

João Paulo Costa

Mike Chou

Proceedings of the 1999 Design, 1999

Interconnect Analysis: From 3-D Structures to Circuit Models.

[BibT_eX]

[DOI]

Yehia Massoud

Proceedings of the 36th Conference on Design Automation, 1999

Robust Rational Function Approximation Algorithm for Model Generation.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

1998

Timing analysis using propositional satisfiability.

[BibT_eX]

[DOI]

João P. Marques Silva

Karem A. Sakallah

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

Efficient Techniques for Accurate Modeling and Simulation of Substrate Coupling in Mixed-Signal IC's.

[BibT_eX]

[DOI]

João Paulo Costa

Mike Chou

Proceedings of the 1998 Design, 1998

A Mixed Nodal-Mesh Formulation for Efficient Extraction and Passive Reduced-Order Modeling of 3D Interconnects.

[BibT_eX]

[DOI]

Proceedings of the 35th Conference on Design Automation, 1998

1996

A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Stability criteria for Arnoldi-based model-order reduction.

[BibT_eX]

[DOI]

Ibrahim M. Elfadel

Proceedings of the 1996 IEEE International Conference on Acoustics, 1996

1995

Efficient reduced-order modeling of frequency-dependent coupling inductances associated with 3-D interconnect structures.

[BibT_eX]

[DOI]

Proceedings of the 1995 European Design and Test Conference, 1995

1994

Model order reduction techniques for circuit simulation.

[BibT_eX]

[DOI]

PhD thesis, 1994

An Efficient Approach to Transmission Line Simulation Using Measured or Tabulated S-parameter Data.

[BibT_eX]

[DOI]

Proceedings of the 31st Conference on Design Automation, 1994

1993

Massively parallel simulation algorithms for grid-based analog signal processors.

[BibT_eX]

[DOI]

Andrew Lumsdaine

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1992

On exponential fitting for circuit simulation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

1991

A Modified Envelope-Following Approach to Clocked Analog Circuit Simulation.

[BibT_eX]

[DOI]

Steven B. Leeb

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1990

Parallel Simulation Algorithms for Grid-Based Analog Signal Processors.

[BibT_eX]

[DOI]

Andrew Lumsdaine