Kristof Blutman

Orcid: 0000-0002-3643-5810

According to our database1, Kristof Blutman authored at least 7 papers between 2013 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2017
Logic Design Partitioning for Stacked Power Domains.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling.
IEEE J. Solid State Circuits, 2017

Floorplan and placement methodology for improved energy reduction in stacked power-domain design.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
A microcontroller with 96% power-conversion efficiency using stacked voltage domains.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Lower power by voltage stacking: a fine-grained system design approach.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2014
A 0.1pJ Freeze Vernier time-to-digital converter in 65nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
A CMOS 0.23pj Freeze Vernier Time-To-Digital Converter.
Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013


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