Nam Sung Woo

According to our database1, Nam Sung Woo authored at least 23 papers between 1983 and 2006.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2006
Promises and challenges of mobile embedded system: : an industry perspective.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

1997
Postlayout logic restructuring using alternative wires.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

1995
Revisiting the Cascade Circuit in Logic Cells of Lookup Table Based FPGAs.
Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

1994
Optimal Routing Algorithms for a Class of Cylindrical Banyan Multicomputers.
J. Parallel Distributed Comput., 1994

Codesign from Cospecification.
Computer, 1994

Layout Driven Logic Synthesis for FPGAs.
Proceedings of the 31st Conference on Design Automation, 1994

1993
The benefits of flexibility in lookup table-based FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

An Efficient Method of Partitioning Circuits for Multiple-FPGA Implementation..
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
The Future of Embedded System Design.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

ORCA: A New Architecture for High-Performance FPLs.
Proceedings of the Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31, 1992

1991
A Heuristic Method for FPGA Technology Mapping Based on the Edge Visibility.
Proceedings of the 28th Design Automation Conference, 1991

1990
A Global, Dynamic Register Allocation and Binding for a Data Path Synthesis System.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989
A cost function based optimization technique for scheduling in data path synthesis.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

A Technology-adaptive Allocation of Functional Units and Connections.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1987
An AND-OR Parallel Execution System for Logic Program Evaluation.
Proceedings of the International Conference on Parallel Processing, 1987

1986
A coment on "A hardware unification unit: design and analysis, ".
SIGARCH Comput. Archit. News, 1986

A reply to comments "a comment on 'a hardware unification unit: design and analysis, '".
SIGARCH Comput. Archit. News, 1986

Selecting the Backtrack Literal in the AND/OR Model.
Proceedings of the 1986 Symposium on Logic Programming, 1986

1985
A Symmetric Tree Structure Interconnection Network and its Message Traffic.
IEEE Trans. Computers, 1985

The architecture of the hardware unification unit and an implementation.
Proceedings of the 18th annual workshop on Microprogramming, 1985

A Hardware Unification Unit: Design and Analysis.
Proceedings of the 12th Annual Symposium on Computer Architecture, 1985

1984
A Proof of the Determinacy Property of the Data Flow Schema.
Inf. Process. Lett., 1984

1983
The DC1 Flow Schema with the Data/Control-Driven Evaluation.
Proceedings of the International Conference on Parallel Processing, 1983


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