Naraig Manjikian

According to our database1, Naraig Manjikian authored at least 36 papers between 1992 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2018
Enhanced Bloom filter utilisation scheme for string matching using a splitting approach.
IET Commun., 2018

2017
A study of maximum frequency in FPGA chips using mesh and toroid circuit topologies.
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017

2016
Retargeting and enhancing a compact multitasking kernel for the Altera Nios II processor.
Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016

2015
Dynamic RAM-based programs and tasks in the freescale MQX operating system.
Proceedings of the IEEE 28th Canadian Conference on Electrical and Computer Engineering, 2015

2014
Automatic generation of parallelized FFT logic for implementation in FPGA chips.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

2013
A hardware test platform in field-programmable logic for parallelized digital signal processing.
Proceedings of the 26th IEEE Canadian Conference on Electrical and Computer Engineering CCECE 2013, 2013

Implementation and performance assessment of Linux device drivers for the coldfire MCF54418 microcontroller.
Proceedings of the 26th IEEE Canadian Conference on Electrical and Computer Engineering CCECE 2013, 2013

A graphical software tool with integer linear programming for microcontroller input/output interface selection feasibility.
Proceedings of the 26th IEEE Canadian Conference on Electrical and Computer Engineering CCECE 2013, 2013

2012
An FPGA implementation for a high-speed optical link with a PCIe interface.
Proceedings of the IEEE 25th International SOC Conference, 2012

Performance optimization of a data transfer controller for parallel matrix multiplication in FPGAS.
Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering, 2012

2011
Controller design for matrix multiplication on FPGAs.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

Analysis and parallelization of JPEG-2000 reference software.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

2010
Reliability- and process variation-aware placement for FPGAs.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Performance optimization and parallelization of turbo decoding for software-defined radio.
Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, 2009

2006
Enhanced Architectural Support for Variable-Length Decoding.
Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006

Enhancements and Applications of a Versatile Software Tool for High-Level Specification of Single-Chip Systems.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

2004
Architecture and Implementation of Chip Multiprocessors: Custom Logic Components and Software for Rapid Prototyping.
Proceedings of the 33rd International Conference on Parallel Processing (ICPP 2004), 2004

2002
Simulation of an Integrated Architecture for IP-over-ATM Frame Processing.
Simul., 2002

2001
Exploiting Wavefront Parallelism on Large-Scale Shared-Memory Multiprocessors.
IEEE Trans. Parallel Distributed Syst., 2001

More enhancements of the simplescalar tool set.
SIGARCH Comput. Archit. News, 2001

Multiprocessor enhancements of the SimpleScalar tool set.
SIGARCH Comput. Archit. News, 2001

Hardware/software tradeoffs for IP-over-ATM frame reassembly in an integrated architecture.
Comput. Commun., 2001

Parallel simulation of multiprocessor execution: implementation and results for simplescalar.
Proceedings of the 2001 IEEE International Symposium on Performance Analysis of Systems and Software, 2001

2000
Optimizing software performance for IP frame reassembly in an integrated architecture.
Proceedings of the Second International Workshop on Software and Performance, 2000

In-lecture hardware demonstrations with a logic analyzer to illustrate pipelined execution and cache/memory behavior.
Proceedings of the 2000 workshop on Computer architecture education, 2000

Enhancements and applications of the SimpleScalar simulator for undergraduate and graduate computer architecture education.
Proceedings of the 2000 workshop on Computer architecture education, 2000


A Vector Multiprocessor for Real-Time Multi-User Detection in Spread-Spectrum Communication.
Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000

1998
Locality Enhancement for Large-Scale Shared-Memory Multiprocessors.
Proceedings of the Languages, 1998

Design and Implementation of the NUMAchine Multiprocessor.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Fusion of Loops for Parallelism and Locality.
IEEE Trans. Parallel Distributed Syst., 1997

Combining Loop Fusion with Prefetching on Shared-memory Multiprocessors.
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

1996
Scheduling of Wavefront Parallelism on Scalable Shared-memory Multiprocessors.
Proceedings of the 1996 International Conference on Parallel Processing, 1996

Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools.
Proceedings of the 33st Conference on Design Automation, 1996

1993
High performance parallel logic simulations on a network of workstations.
Proceedings of the Seventh Workshop on Parallel and Distributed Simulation, 1993

1992
Using split event sets to form and schedule event combinations in discrete event simulation.
Proceedings of the Proceedings 25th Annual Simulation Symposium (ANSS-25 1992), 1992


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