Zvonko G. Vranesic

According to our database, Zvonko G. Vranesic authored at least 78 papers between 1970 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2013

Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAs.

Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown

ACM Trans. Reconfigurable Technol. Syst., 2013

2009

Enhancements to FPGA design methodology using streaming.

Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008

Stream Programming for FPGAs.

Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown

Proceedings of the Languages for Embedded Systems and their Applications, 2008

Towards Compilation of Streaming Programs into FPGA Hardware.

Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown

Proceedings of the Forum on specification and Design Languages, 2008

2007

On Digital Search Trees - A Simple Method for Constructing Balanced Binary Trees.

Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown

Proceedings of the ICSOFT 2007, 2007

2006

Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping.

Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Adaptive FPGAs: High-Level Architecture and a Synthesis Method.

Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

A Multithreaded Soft Processor for SoPC Area Reduction.

Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown

Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

2005

Experiences with Soft-Core Processor Design.

Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen Dean Brown

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2003

A fast algorithm for OR-AND-OR synthesis.

Debatosh Debnath, Zvonko G. Vranesic

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Use of HDLs in teaching of computer hardware courses.

Zvonko G. Vranesic, Stephen Dean Brown

Proceedings of the 2003 workshop on Computer architecture education, 2003

2002

A Deterministic Multivariate Interpolation Algorithm for Small Finite Fields.

Zeljko Zilic, Zvonko G. Vranesic

IEEE Trans. Computers, 2002

Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices.

Valavan Manohararajah, Terry P. Borer, Stephen Dean Brown, Zvonko G. Vranesic

Proceedings of the Field-Programmable Logic and Applications, 2002

2001

Structural analysis and generation of synthetic digital circuits with memory.

Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic

IEEE Trans. Very Large Scale Integr. Syst., 2001

2000

The NUMAchine Multiprocessor.

R. Grindley, Tarek S. Abdelrahman, Stephen Dean Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic

Proceedings of the 2000 International Conference on Parallel Processing, 2000

1999

The memory/logic interface in FPGAs with large embedded memory arrays.

Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic

IEEE Trans. Very Large Scale Integr. Syst., 1999

The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning.

Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic

Int. J. Parallel Program., 1999

1998

Using Decision Diagrams to Design ULMs for FPGAs.

Zeljko Zilic, Zvonko G. Vranesic

IEEE Trans. Computers, 1998

The FPGA Challenge.

Zvonko G. Vranesic

Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

Design and Implementation of the NUMAchine Multiprocessor.

A. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic

Proceedings of the 35th Conference on Design Automation, 1998

1997

Analytical Prediction of Performance for Cache Coherence Protocols.

Sinisa Srbljic, Zvonko G. Vranesic, Michael Stumm, Leo Budin

IEEE Trans. Computers, 1997

The Multicluster Architecture: Reducing Cycle Time Through Partitioning.

Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic

Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997

Memory-System Design Considerations for Dynamically-Scheduled Processors.

Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic

Proceedings of the 24th International Symposium on Computer Architecture, 1997

Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays.

Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic

Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, 1997

1996

Minimizing FPGA Interconnect Delays.

Stephen Dean Brown, Muhammad M. Khellah, Zvonko G. Vranesic

IEEE Des. Test Comput., 1996

New Interpolation Algorithms for Multiple-Valued Reed-Muller Forms.

Zeljko Zilic, Zvonko G. Vranesic

Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996

Using BDDs to Design ULMs for FPGAs.

Zeljko Zilic, Zvonko G. Vranesic

Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996

Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools.

Stephen Dean Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic

Proceedings of the 33st Conference on Design Automation, 1996

1995

Scalable cache consistency for hierarchically structured multiprocessors.

Keith I. Farkas, Zvonko G. Vranesic, Michael Stumm

J. Supercomput., 1995

A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions.

Zeljko Zilic, Zvonko G. Vranesic

IEEE Trans. Computers, 1995

Reed-Muller Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation.

Zeljko Zilic, Zvonko G. Vranesic

Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995

Architecture of Centralized Field-Configurable Memory.

Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic

Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

Bidirectional Ring: An Alternative to the Hierarchy of Unidirectional Rings.

Muhammad Jaseemuddin, Zvonko G. Vranesic

Proceedings of the Euro-Par '95 Parallel Processing, 1995

1994

On Scheduling in Multiprocessor Systems Using Fuzzy Logic.

Alireza Kaviani, Zvonko G. Vranesic

Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

Performance Prediction for Different Consistency Schemes in Distributed Shared Memory Systems.

Sinisa Srbljic, Zvonko G. Vranesic, Leo Budin

Proceedings of the Third International Symposium on High Performance Distributed Computing, 1994

1993

A stochastic model to predict the routability of field-programmable gate arrays.

Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Physically Based Modeling and Control of Turning.

Michiel van de Panne, Eugene Fiume, Zvonko G. Vranesic

CVGIP Graph. Model. Image Process., 1993

Architectural Support for Block Transfers in a Shared-Memory Multiprocessor.

Steven J. E. Wilton, Zvonko G. Vranesic

Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993

Current-Mode CMOS Galois Field Circuits.

Zeljko Zilic, Zvonko G. Vranesic

Proceedings of the 23rd IEEE International Symposium on Multiple-Valued Logic, 1993

1992

A detailed router for field-programmable gate arrays.

Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Cache Consistency in Hierarchical-Ring-Based Multiprocessors.

Keith I. Farkas, Zvonko G. Vranesic, Michael Stumm

Proceedings of the Proceedings Supercomputing '92, 1992

Towards the Realization of 4-Valued CMOS Circuits.

Konrad Lei, Zvonko G. Vranesic

Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992

1991

Algorithmic Synthesis of MVL Functions for CCD Implementation.

Mostafa I. H. Abd-El-Barr, Zvonko G. Vranesic, Safwat G. Zaky

IEEE Trans. Computers, 1991

Hector: A Hierarchically Structured Shared-memory Multiprocessor.

Zvonko G. Vranesic, Michael Stumm, David M. Lewis, Ron White

Computer, 1991

On the Synthesis of 4-Valued Current Mode CMOS Circuits.

Konrad Lei, Zvonko G. Vranesic

Proceedings of the 21st International Symposium on Multiple-Valued Logic, 1991

A Hybrid Token/Insertion Ring LAN.

Zvonko G. Vranesic, V. Carl Hamacher, A. K. Sanwalka, Safwat G. Zaky

Proceedings of the Proceedings IEEE INFOCOM '91, 1991

Technology Mapping on Lookup Table-Based FPGAs for Performance.

Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs.

Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic

Proceedings of the 28th Design Automation Conference, 1991

1990

Cost Reduction in the CCD Realization of MVMT Function.

Mostafa I. H. Abd-El-Barr, Zvonko G. Vranesic

IEEE Trans. Computers, 1990

Reusable motion synthesis using state-space controllers.

Michiel van de Panne, Eugene Fiume, Zvonko G. Vranesic

Proceedings of the 17th Annual Conference on Computer Graphics and Interactive Techniques, 1990

Step-Wise Synthesis of CCD MVL Functions.

Safwat G. Zaky, Zvonko G. Vranesic, Mostafa I. H. Abd-El-Barr

Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990

TORMLAN - A Multichannel Local Area Network Protocol.

Lap-kong Chan, Zvonko G. Vranesic

Proceedings of the Proceedings IEEE INFOCOM '90, 1990

Computer organization, 3rd Edition.

V. Carl Hamacher, Zvonko G. Vranesic, Safwat G. Zaky

McGraw-Hill computer science series, McGraw-Hill, ISBN: 978-0-07-025685-9, 1990

1989

Using active components to perform voltage division in digital-to-analog conversion.

Chu Phoon Chong, Kenneth C. Smith, Zvonko G. Vranesic

IEEE J. Solid State Circuits, August, 1989

1988

Parallel standard cell placement algorithms with quality equivalent to simulated annealing.

Jonathan Rose, W. Martin Snelgrove, Zvonko G. Vranesic

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

1986

Synthesis of Multivalued Multithreshold Functions for CCD Implementation.

Mostafa I. H. Abd-El-Barr, Safwat G. Zaky, Zvonko G. Vranesic

IEEE Trans. Computers, 1986

Implementation of a Dynamic Address Assignment Protocol in a Local Area Network.

Wayne M. Loucks, William I. Kwak, Zvonko G. Vranesic

Comput. Networks, 1986

1985

FERMTOR: A Tunable Multiprocessor Architecture.

Jonathan Rose, Wayne M. Loucks, Zvonko G. Vranesic

IEEE Micro, 1985

1984

Comments on "Fault Diagnosis of MOS Combinational Networks".

Kuang-Wei Chiang, Zvonko G. Vranesic

IEEE Trans. Computers, 1984

1983

A Pipelined Distributed Arithmetic PFFT Processor.

Paul Chow, Zvonko G. Vranesic, Jui Lin Yen

IEEE Trans. Computers, 1983

A Tree Representation of Combinational Networks.

Kuang-Wei Chiang, Zvonko G. Vranesic

IEEE Trans. Computers, 1983

On fault detection in CMOS logic networks.

Kuang-Wei Chiang, Zvonko G. Vranesic

Proceedings of the 20th Design Automation Conference, 1983

1981

Key compression using segment strings.

C. L. Lam, Zvonko G. Vranesic

Inf. Syst., 1981

TORNET: A local area network.

Zvonko G. Vranesic, V. Carl Hamacher, Wayne M. Loucks, Safwat G. Zaky

Proceedings of the seventh symposium on Data communications, 1981

1980

Ternary Rate-Multipliers.

Hussein T. Mouftah, Kenneth C. Smith, Zvonko G. Vranesic

IEEE Trans. Computers, 1980

Teaching Computer Structures.

Zvonko G. Vranesic, Kenneth J. Thurber, Sperry Univac

Computer, 1980

1978

A. Higher Radix Technique for Fault Detection in Many-Valued Multithreshold Networks.

A. Druzeta, Zvonko G. Vranesic

IEEE Trans. Computers, 1978

Review of Content addressable parallel processors by Caxton C. Foster. Van Nostrand Reinhold Co. 1976.

Zvonko G. Vranesic

SIGARCH Comput. Archit. News, 1978

1977

Multiple-Valued Logic: An Introduction and Overview.

Zvonko G. Vranesic

IEEE Trans. Computers, 1977

Experiences with CHUTE.

F. M. Valenti, Zvonko G. Vranesic

Proceedings of the 1977 annual conference, 1977

1974

Fault Detection of Binary Sequential Machines Using R-Valued Test Machines.

Donald A. Sheppard, Zvonko G. Vranesic

IEEE Trans. Computers, 1974

Application of Multithreshold Elements in the Realization of Many-Valued Logic Networks.

A. Druzeta, Zvonko G. Vranesic, A. S. Sedra

IEEE Trans. Computers, 1974

Engineering aspects of multi-valued logic systems.

Zvonko G. Vranesic, Kenneth C. Smith

Computer, 1974

1973

Design of a Fully Variable - Length Structured Minicomputer.

Zvonko G. Vranesic, V. Carl Hamacher, Y. Y. Leung

Proceedings of the 1st Annual Symposium on Computer Architecture, 1973

1972

Functional Transformation in Simplification of Multivalued Switching Functions.

Zvonko G. Vranesic, K. M. Waliuzzaman

IEEE Trans. Computers, 1972

Ternary logic in parallel multipliers.

Zvonko G. Vranesic, V. Carl Hamacher

Comput. J., 1972

1970

A Many-Valued Algebra for Switching Systems.

Zvonko G. Vranesic, E. Stewart Lee, Kenneth C. Smith

IEEE Trans. Computers, 1970

On Decomposition of Multi-Valued Switching Functions.

K. M. Waliuzzaman, Zvonko G. Vranesic

Comput. J., 1970