Shervin Vakili

Orcid: 0000-0002-4791-9298

According to our database1, Shervin Vakili authored at least 17 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

Online presence:

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Bibliography

2023
Fast and Low-Cost Approximate Multiplier for FPGAs using Dynamic Reconfiguration.
CoRR, 2023

A Cost-Effective FPGA-Based Approximate Multiplier for Machine Learning Acceleration.
Proceedings of the 14th IEEE International Symposium on Parallel Architectures, 2023

2021
CARLA: A Convolution Accelerator With a Reconfigurable and Low-Energy Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020
Heterogeneous Distributed SRAM Configuration for Energy-Efficient Deep CNN Accelerators.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

An Energy-Efficient Accelerator Architecture with Serial Accumulation Dataflow for Deep CNNs.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

2018
Enhanced Bloom filter utilisation scheme for string matching using a splitting approach.
IET Commun., 2018

Power Reduction in CNN Pooling Layers with a Preliminary Partial Computation Strategy.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

2017
Scalable memory-less architecture for string matching with FPGAs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Accuracy-aware processor customisation for fixed-point arithmetic.
IET Comput. Digit. Tech., 2016

Memory-Efficient String Matching for Intrusion Detection Systems using a High-Precision Pattern Grouping Algorithm.
Proceedings of the 2016 Symposium on Architectures for Networking and Communications Systems, 2016

2015
Designing customized microprocessors for fixed-point computation.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

2013
Enhanced Precision Analysis for Accuracy-Aware Bit-Width Optimization Using Affine Arithmetic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Customised soft processor design: a compromise between architecture description languages and parameterisable processors.
IET Comput. Digit. Tech., 2013

Finite-precision error modeling using affine arithmetic.
Proceedings of the IEEE International Conference on Acoustics, 2013

2011
Customized embedded processor design for global photographic tone mapping.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010
Evolvable multi-processor: A novel MPSoC architecture with evolvable task decomposition and scheduling.
IET Comput. Digit. Tech., 2010

Parallel scalable hardware implementation of asynchronous discrete particle swarm optimization.
Eng. Appl. Artif. Intell., 2010


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