Narendra Devta-Prasanna

According to our database1, Narendra Devta-Prasanna authored at least 24 papers between 2005 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2014
Hybrid/Top-off Test Pattern Generation Schemes for Small-Delay Defects.
Proceedings of the Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits., 2014

Small-Delay Defect Coverage Metrics.
Proceedings of the Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits., 2014

2012
A novel method for fast identification of peak current during test.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Silicon evaluation of faster than at-speed transition delay tests.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

2010
Multiple fault activation cycle tests for transistor stuck-open faults.
Proceedings of the 2011 IEEE International Test Conference, 2010

Clock Gate Test Points.
Proceedings of the 2011 IEEE International Test Conference, 2010

2009
Effective and Efficient Test Pattern Generation for Small Delay Defect.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: A simulation and silicon study.
Proceedings of the 2009 IEEE International Test Conference, 2009

Accurate measurement of small delay defect coverage of test patterns.
Proceedings of the 2009 IEEE International Test Conference, 2009

Improving the Detectability of Resistive Open Faults in Scan Cells.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Detectability of internal bridging faults in scan chains.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Comparative study of centralised and distributed compatibility-based test data compression.
IET Comput. Digit. Tech., 2008

On the Detectability of Scan Chain Internal Faults - An Industrial Case Study.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Detection of Internal Stuck-open Faults in Scan Chains.
Proceedings of the 2008 IEEE International Test Conference, 2008

An Enhanced Logic BIST Architecture for Online Testing.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007
Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Systematic Scan Reconfiguration.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults.
Proceedings of the 11th European Test Symposium, 2006

Test Generation for Open Defects in CMOS Circuits.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005
Methods for improving transition delay fault coverage using broadside tests.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Should Illinois-Scan Based Architectures be Centralized or Distributed?
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005


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